A 32-bit microprocessor with efficient testable designs, the TX2

Abstract

A 32-bit microprocessor, the T X 2 , with efficien.2 testable designs, has been developed. For manufacturing test, a combinaiion of powerful BISTs and parallel scan design is implemented. The BISTs achieze 100% funciional coverage for ROM, RAM and P L A and 78%: coverage of single stuck-at faults of the remaining pari of ihe T X 2 including redundant faults. Scan test vectors obtained b y A T P G have enhanced the corerage i o 84%. Total lest time is less ihan 2 seconds. There are also a few circuitry for efficient design zerification. Moreover, f o r higher test quality, Idd,q test is implemented. Total area overhead is 6.9%