Impedance Adapting Compensation for Low-Power Multistage Amplifiers

Peng, Xiaohong; Sansen, Willy; Hou, Ligang; Wang, Jinhui; Wu, Wuchen

doi:10.1109/jssc.2010.2090088

Cited by 104 publications

(96 citation statements)

References 18 publications

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“…15, both the 3-step and 4-step NCM amplifiers achieve comparable , and break the limit of largedrivability. Before we apply any dynamic-biasing SR-enhancement technique [28], [29], the of the 4-step NCM amplifier is still 2.2 higher than [22], but 1.2 , 1.47 , 5.8 and 9.79 lower than [24]- [27], respectively. [26] and [27] have better owing to the added SR helper and aggressively scaled compensation capacitors, respectively, whereas both have a limited -drivability range.…”

Section: Resultsmentioning

confidence: 97%

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Nested-Current-Mirror Rail-to-Rail-Output Single-Stage Amplifier With Enhancements of DC Gain, GBW and Slew Rate

Zhang

Mak

Law

et al. 2015

IEEE J. Solid-State Circuits

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For better area and power efficiencies, rail-to-railoutput single-stage amplifiers are a potential replacement of their multi-stage counterparts, especially for display applications that entail massive buffer amplifiers in their column drivers. This paper describes a nested-current-mirror (NCM) technique for a single-stage amplifier to achieve substantial enhancements of DC gain, gain-bandwidth product (GBW) and slew rate (SR). Specifically, NCM is customizable for different mirror steps, and sub mirror ratios, to balance the performance metrics and capacitive-load ( ) drivability, avoiding any compensation passives while preserving a rail-to-rail output swing. Analytical treatments of the NCM technique in terms of performance limits and robustness reveal that the NCM amplifier can surpass the fundamental power-efficiency limit set by the basic differential-pair (DP) amplifier. Two prototypes, 3-step and 4-step NCM amplifiers, were fabricated in 0.18 m CMOS for systematic comparison with the DP amplifier. The former represents a robust design exhibiting 72 dB DC gain and 0.0028-0.27 MHz GBW over 0.15-15 nF with 80 phase margin (PM). The latter embodies an aggressive design attaining 84 dB DC gain and 0.013-1.24 MHz GBW over 0.15-15 nF with 62 PM. All amplifiers were sized for the same area (0.0013 mm ) and power (3.6 W).Index Terms-Area efficiency, CMOS, current mirror, DC gain, differential-pair (DP) amplifier, frequency compensation, gain-bandwidth product (GBW), low temperature polysilicon LCD, multi-stage amplifier, nested current mirror, rail-to-rail output swing, single-stage amplifier, slew rate (SR), stability.

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Section: Resultsmentioning

confidence: 97%

“…Unlike the multi-stage amplifiers, no bulky passives are entailed in our single-stage solutions. To allow a fair comparison with recent three-stage amplifiers [22]- [27], two figuresof-merit (FOMs) [5] that account for the impact of both power and area: and , are introduced. As summarized in Fig.…”

Section: Resultsmentioning

confidence: 99%

Nested-Current-Mirror Rail-to-Rail-Output Single-Stage Amplifier With Enhancements of DC Gain, GBW and Slew Rate

Zhang

Mak

Law

et al. 2015

IEEE J. Solid-State Circuits

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“…Further, Table 5-9 also suggests that the RNIC requires lower power compared to NMCNR, for the same target design specifications. The commonly used small-signal FoM, FoM S [105], indicates the superior performance of the RNIC technique. …”

Section: Nmcnr Stabilizationmentioning

confidence: 99%

Low-Voltage Analog-to-Digital Converters and Mixed-Signal Interfaces

Harikumar¹

2016

Linköping Studies in Science and Technology. Dissertations

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Analog-to-digital converters (ADCs) are crucial blocks which form the interface between the physical world and the digital domain. ADCs are indispensable in numerous applications such as wireless sensor networks (WSNs), wireless/wireline communication receivers and data acquisition systems. To achieve long-term, autonomous operation for WSNs, the nodes are powered by harvesting energy from ambient sources such as solar energy, vibrational energy etc. Since the signal frequencies in these distributed WSNs are often low, ultra-low-power ADCs with low sampling rates are required. The advent of new wireless standards with ever-increasing data rates and bandwidth necessitates ADCs capable of meeting the demands. Wireless standards such as GSM, GPRS, LTE and WLAN require ADCs with several tens of MS/s speed and moderate resolution (8-10 bits). Since these ADCs are incorporated into battery-powered portable devices such as cellphones and tablets, low power consumption for the ADCs is essential.The first contribution is an ultra-low-power 8-bit, 1 kS/s successive approximation register (SAR) ADC that has been designed and fabricated in a 65-nm CMOS process. The target application for the ADC is an autonomously-powered soil-moisture sensor node. At V DD = 0.4 V, the ADC consumes 717 pW and achieves an FoM = 3.19 fJ/conv-step while meeting the targeted dynamic and static performance. The 8-bit ADC features a leakage-suppressed S/H circuit with boosted control voltage which achieves > 9-bit linearity. A binary-weighted capacitive array digital-to-analog converter (DAC) is employed with a very low, custom-designed unit capacitor of 1.9 fF. Consequently the area of the ADC and power consumption are reduced. The ADC achieves an ENOB of 7.81 bits at near-Nyquist input frequency. The core area occupied by the ADC is only 0.0126 mm 2 .The second contribution is a 1.2 V, 10 bit, 50 MS/s SAR ADC designed and implemented in 65 nm CMOS aimed at communication applications. For medium-tohigh sampling rates, the DAC reference settling poses a speed bottleneck in chargeredistribution SAR ADCs due to the ringing associated with the parasitic inductances. Although SAR ADCs have been the subject of intense research in recent years, scant attention has been laid on the design of high-performance on-chip reference voltage buffers. The estimation of important design parameters of the buffer as well iv critical specifications such as power-supply sensitivity, output noise, offset, settling time and stability have been elaborated upon in this dissertation. The implemented buffer consists of a two-stage operational transconductance amplifier (OTA) combined with replica source-follower (SF) stages. The 10-bit SAR ADC utilizes split-array capacitive DACs to reduce area and power consumption. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the ...

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“…The LHP zero generated by the transconductance g mf1 , is used to cancel the negative phase shift of the first non-dominant pole. Since this cancelation takes place beyond the unity gain frequency, its effect on the settling time is marginal [16]. The targeted pole-zero distributions are shown in Fig.…”

Section: Architectures Of the Proposed Amplifiersmentioning

confidence: 99%

“…Also, some advanced techniques use active feedbacks to create high speed paths and improve the bandwidth [1,[8][9][10]14]. In order to further enhance the gain-bandwidth product, other techniques such as multipath NMC (MNMC) [15], impedance adapting compensation (IAC) [16], and no capacitor feedforward (NCFF) [17], generate left half plane (LHP) zeros and perform pole-zero cancelations. The pole elimination improves the phase response and sufficient phase margin is possible with larger unity gain frequencies.…”

Section: Introductionmentioning

confidence: 99%