Impacts of Random Telegraph Noise (RTN) on Digital Circuits

Abstract

Random telegraph noise (RTN) is one of the important dynamic variation sources in ultrascaled MOSFETs. In this paper, the recently focused ac trap effects of RTN in digital circuits and their impacts on circuit performance are systematically investigated. Instead of trap occupancy probability under dc bias condition ( p dc ), which is traditionally used for RTN characterization, ac trap occupancy probability ( p ac ), i.e., the effective percentage of time trap being occupied under ac bias condition, is proposed and evaluated analytically to investigate the dynamic trapping/detrapping behavior of RTN. A simulation approach that fully integrates the dynamic properties of ac trap effects is presented for accurate simulation of RTN in digital circuits. The impacts of RTN on digital circuit performances, e.g., failure probabilities of SRAM cells and jitters of ring oscillators, are then evaluated by the simulations and verified against predictions based on p ac . The results show that degradations are highly workload dependent and that p ac is critical in accurately evaluating the RTN-induced performance degradation and variability. The results are helpful for robust and resilient circuit design. Index Terms-Bit error rate (BER), dynamic variability, failure probability, Monte Carlo simulation, oxide trap, random telegraph noise (RTN), ring oscillator, signal integrity, SRAM.

On the Accuracy in Modeling the Statistical Distribution of Random Telegraph Noise Amplitude

“…The number of traps per device follows the Poisson distribution [3]- [6]. To perform Monte Carlo simulation in the time domain, one needs the captureemission times and RTN amplitude of traps [5], [18], [22], [23]. We studied the statistical distribution of capture/emission time constants in an early work [18] and focus on the amplitude distribution here.…”

An Assessment of the Statistical Distribution of Random Telegraph Noise Time Constants

“…To take RTN into account when optimizing circuit design, substantial efforts have been made to model RTN [6]- [11]. For dynamic Monte Carlo modelling, one needs the statistical distributions of the number of traps per device, the amplitude of RTN per trap, and the capture/emission time (CET) of traps [3], [11], [12].…”

“…To take RTN into account when optimizing circuit design, substantial efforts have been made to model RTN [6]- [11]. For dynamic Monte Carlo modelling, one needs the statistical distributions of the number of traps per device, the amplitude of RTN per trap, and the capture/emission time (CET) of traps [3], [11], [12]. Early works [9], [13] have focused their attentions on the amplitude distributions and the CET distribution has been rarely reported based on test data [1], [14]- [17].…”

A Dual-Point Technique for the Entire ID–VG Characterization Into Subthreshold Region Under Random Telegraph Noise Condition

“…However, the standard RTN procedure [4] only captures the current under constant gate voltage, VG_RTN, which contains limited information. Understanding the entire ID-VG curve and its shift induced by the Random Telegraph Noise (RTN) can provide valuable information in understanding its underlying physical mechanism [5][6][7] and also in the circuit simulation for the time-dependent variability prediction [8,9]. Usually such measurement is carried out by repeating the standard RTN test procedure under different VG levels [10,11].…”