Impacts of Process and Temperature Variations on the Crosstalk Effects in Sub-10 nm Multilayer Graphene Nanoribbon Interconnects

Hamedani, Soheila Gharavi; Moaiyeri, Mohammad Hossein

doi:10.1109/tdmr.2019.2937789

Cited by 27 publications

(7 citation statements)

References 45 publications

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“…Consequently, as the resistance is the dominant factor in determining the number and size of repeaters (see Eqs. [15][16][17][18][19][20], the MLGNR interconnect has a smaller N opt and a greater S opt .…”

Section: Results and Analysismentioning

confidence: 99%

“…The critical physical parameters of the interconnects and CNTFETs considered for the Monte Carlo simulations, along with their nominal values and variations, are given in Table VI. 19,49 It is noteworthy that to have more fair and precise evaluations and comparisons, we have considered the process parameters common between MWCNT and MLGNR interconnects. The maximum variations of the delay and PDP of the interconnects with 1000 μm length in the presence of all process variations are shown in Figs.…”

Section: Results and Analysismentioning

confidence: 99%

“…The controllability of the threshold voltage of CNTFETs by changing the flat band voltage is a significant attribute that has led to the widespread use of CNTFETs in multiple-valued logic (MVL), specifically ternary designs. [17][18][19] Ternary logic has been studied for several years as it can provide significant advantages to decrease the number of wires and reduce the complexity of arithmetic operations. Additionally, ternary interconnects can transmit more information than their binary counterparts.…”

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confidence: 99%

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Crosstalk Delay and Noise Optimization in Nanoscale Multi-line Interconnects Based on Repeater Staggering in Ternary Logic

Hamedani

Moaiyeri

2021

ECS J. Solid State Sci. Technol.

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In this study, the crosstalk effects are minimized in coupled multi-line wires based on repeater staggering in ternary logic. For more accuracy, the impact of the coupling capacitance is also considered in our calculations. Our results indicate that the number of repeaters required for optimizing the delay of the multilayer graphene nanoribbon (MLGNR) interconnect is, on average, 43% lower than multi-walled carbon nanotube (MWCNT) interconnect. Moreover, the optimized delay of the MLGNR interconnect is, on average, 48% lower than MWCNT interconnect. The ternary repeater insertion reduces the delay of the MWCNT and MLGNR interconnects carrying ternary signals by 61% and 51%, respectively. The staggered repeater insertion is applied as a practical approach for eliminating the crosstalk noise in the transmitted ternary signals in a multi-line coupled structure. Our results demonstrate that the delay and energy of the staggered repeater-inserted MLGNR interconnects are, on average, 42% and 37% lower than their MWCNT counterparts. Furthermore, the impacts of the process variations are investigated using comprehensive Monte Carlo simulations and the optimized ternary multi-line MLGNR interconnect functions correctly and considerably robustly compared to their MWCNT counterpart.

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Section: Results and Analysismentioning

confidence: 99%

Section: Results and Analysismentioning

confidence: 99%

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confidence: 99%

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Crosstalk Delay and Noise Optimization in Nanoscale Multi-line Interconnects Based on Repeater Staggering in Ternary Logic

Hamedani

Moaiyeri

2021

ECS J. Solid State Sci. Technol.

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“…The interconnection lines used in integrated circuit design increase the delay, noise, and power consumption of the system, so circuit interconnection has become one of the essential indicators to judge the performance of integrated circuit systems. [1] There are only two logic states of '0' and '1' in traditional binary logic. Multi-valued logic is extended from binary logic, referring to the logic that the number of the logic values is greater than 2.…”

Section: Introductionmentioning

confidence: 99%

A review on the design of ternary logic circuits*

Wang

Dong

2021

Chinese Phys. B

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A multi-valued logic system is a promising alternative to traditional binary logic because it can reduce the complexity, power consumption, and area of circuit implementation. This article briefly summarizes the development of ternary logic and its advantages in digital logic circuits. The schemes, characteristics, and application of ternary logic circuits based on CMOS, CNTFET, memristor, and other devices and processes are reviewed in this paper, providing some reference for the further research and development of ternary logic circuits.

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“…Moreover, the traditional copper wires have faced many critical challenges in deep nanoscale nodes such as surface scattering, grain boundaries, dishing and erosion effects, high-power density, and electromigration. 2 Utilizing promising emerging nanodevices such as carbon nanotube field-effect transistors (CNTFETs) 1,3 and interconnects such as carbon nanotube (CNT) and graphene nanoribbon (GNR) can address the critical issues of modern chips in sub-10nm nodes. 2,4,5 Single-walled carbon nanotube (SWCNT) consists of a single cylindrical sheet of graphene and is commonly used as the channel region in CNTFETs.…”

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confidence: 99%

An Energy-Efficient Crosstalk Reduction Strategy for On-Chip Buses Using Carbon-Based Transistors and Interconnects

Azimi

Moaiyeri

Hamedani

2021

ECS J. Solid State Sci. Technol.

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This paper presents a novel crosstalk reduction scheme based on quaternary logic that eliminates the harmful transition patterns and protects communication channels of system-on-chips (SoCs) against crosstalk. The proposed architecture is designed based on gate-all-around carbon nanotube field-effect transistor (GAA-CNTFET) codec and converter modules considering multi-walled carbon nanotube (MWCNT), and multilayer graphene nanoribbon (MLGNR) interconnects at 10 nm technology. The simulation results indicate that our proposed approach reduces the delay and power-delay product (PDP) on average by 52% and 36%, respectively, for MWCNT interconnects compared to the basic architecture. These improvements are 50% and 35% for the MLGNR interconnects. Moreover, utilizing the MLGNR interconnects instead of MWCNT interconnects in the proposed coded system leads to a 61% shorter crosstalk delay and 65% lower PDP. In addition, the proposed coding scheme leads to 35% reduction in the occupied area and improves PDP, on average, by 37%, and 26% for the MWCNT and MLGNR buses, respectively, as compared to their binary counterparts.

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Impacts of Process and Temperature Variations on the Crosstalk Effects in Sub-10 nm Multilayer Graphene Nanoribbon Interconnects

Cited by 27 publications

References 45 publications

Crosstalk Delay and Noise Optimization in Nanoscale Multi-line Interconnects Based on Repeater Staggering in Ternary Logic

Crosstalk Delay and Noise Optimization in Nanoscale Multi-line Interconnects Based on Repeater Staggering in Ternary Logic

A review on the design of ternary logic circuits*

An Energy-Efficient Crosstalk Reduction Strategy for On-Chip Buses Using Carbon-Based Transistors and Interconnects

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