Extended Abstracts of International Workshop on Gate Insulator (IEEE Cat. No.03EX765) 2003
DOI: 10.1109/iwgi.2003.159188
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Impacts of hole trapping on the NBTI degradation and recovery in PMOS devices

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Cited by 5 publications
(2 citation statements)
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“…This effect originated from the fact that the gate edge region is more affected by the fabrication process, such as gate etching [4], which enhance pre-existing damage located near the channel edges. It has been considered by some authors [9] that the generation of interface traps is higher near the gate edge region and some others thought that the oxides traps increases with decreasing channel length [10]. In this work, the NBTI effect has been investigated in P and N-substrate MOS capacitors.…”
Section: Introductionmentioning
confidence: 99%
“…This effect originated from the fact that the gate edge region is more affected by the fabrication process, such as gate etching [4], which enhance pre-existing damage located near the channel edges. It has been considered by some authors [9] that the generation of interface traps is higher near the gate edge region and some others thought that the oxides traps increases with decreasing channel length [10]. In this work, the NBTI effect has been investigated in P and N-substrate MOS capacitors.…”
Section: Introductionmentioning
confidence: 99%
“…Lin et al also indicate that the re-passivation of interface traps has small contribution to the recovery of threshold voltage shift, while the de-trapping of trapped holes during the relaxation period is the main reason of the recovery [57]. Huard et al [51] also concluded that the recovery of threshold voltage shift is primarily due to detrapping of holes captured by the nitrogen-related centers in the oxide, but not due to the re-passivation of interface traps.…”
Section: 34-2 Deviation From R-d Modelmentioning
confidence: 99%