Impact of Work Function Optimized S/D Silicide Contact for High Current Drivability CMOS

Abstract

A formation process of the silicide/Si contact with low contact resistance in the source/drain (S/D) regions has been developed in order to reduce the S/D electrode series resistance of MOSFETs. Er that has a low Schottky barrier height (SBH) for electrons and Pd that has a low SBH for holes were selected to n + -and p + -Si, respectively. The silicide formation processes were carried out in N 2 ambient from the Si-surface cleaning before the metal depositions to the silicidation anneal in order not to expose metal and Si region so as to prevent the oxidation. A W capping layer was formed on the Er-surface to prevent it from oxidation, since it is very easily oxidized because of its low work function. These silicides were applied to Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs), which improved the current drivability of n-and p-MOSFET due to the reduction of the S/D electrodes series resistance.

Evaluating Work-Function and Composition of ErSixon Various Surface Orientation of Silicon

“…We have also reported that the low barrier height material on Si(100) surface for n + and p + -Si by using the rare metal silicide such as HoSi 2 , YSi 2 , and ErSi 2 and Pd 2 Si, respectively, [23][24][25][26][27] and we have reported that the high performance MOSFET with low contact resistance by using ErSi 2 and Pd 2 Si on the Si(100) surface, and in the resistivity of ErSi 2 and Pd 2 Si on the n + -and p + -Si(100) surface are 6.9 × 10 −9 • cm 2 and 8.0 × 10 −10 • cm 2 , respectively. 19,25 This indicates that the ErSi 2 has possibility for the formation of low contact resistance on the silicon surfaces. Recently, the surface orientation except Si(100) and three-dimensional structures are proposed and fabricated for the improvement of transistor performance.…”

“…It has been reported that R S must be reduced to about 10 • μm for maintaining I D of 1 mA/μm at the 45 nm generation MOSFETs. 19 Here, the components of the series resistance are the source/drain contact resistance and the resistance of lightly doped region under the side wall. This R S of 20 • μm is equivalent to contact resistivity of 9 × 10 −9 • cm 2 for the 45 nm × 1 μm contact holes, which is relatively lower than the conventional value around 10 −8 • cm 2 .…”

In-Depth Analysis on Self Alignment Effect of the Fermi-Level Using Graphene on Both n- and p-Type Semiconductors

“…However, the valence band offset (VBO) should be considered for p-type semiconductors (p-type SCs) to facilitate hole transfer. Therefore, existing MIS techniques suggest different contact schemes for each type of semiconductor, challenging the application of a single integrated contact structure. − Moreover, the use of metals in the MIS contact structures is limited. With the FL unpinned, the number of metals that offer low contact resistance is small.…”

Electrical Properties of Silicon Nitride Using High Density and Low Plasma Damage PECVD Formed at 400ºC

“…In order to improve the performance of metal oxide semiconductor field effect transistors (MOSFETs) in the scaled down generation, integration of various new materials has been studied such as high dielectric constant materials and metal gate materials and silicide materials (1)(2)(3)(4)(5)(6)(7)(8)(9). Thin insulator films to protect these materials from various chemical solutions during integration process are required in order to avoid the chemical instability of these materials.…”

“…It has been reported that the quality of silicon nitride at the sidewall is compatible to the quality of silicon nitride on the blank Si by the plasma enhanced chemical vapor deposition (PECVD) using the microwave excited high density plasma that can produce a high plasma density more than 10 11 cm -3 at low ion energy less than 2 eV at 400 o C in order to apply to the gate spacer, the silicide block layer and the contact etching stop layer (13)(14)(15)(16). Silicon nitride is deposited using Ar/N 2 /H 2 /SiH 4 gases.…”