Impact of Variability on Processor Performance in Negative Capacitance FinFET Technology

Amrouch, Hussam; Pahwa, Girish; Gaidhane, Amol D.; Dabhi, Chetan Kumar; Klemme, Florian; Prakash, Om; Chauhan, Yogesh Singh

doi:10.1109/tcsi.2020.2990672

Cited by 49 publications

(18 citation statements)

References 21 publications

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“…(1) Process Variation Effects: First, we would like to mention that even through the presented analysis in this manuscript is only for the MADD circuit (which is a digital circuit), the characterized NCFET-aware cell library contains a wide range of different standard cell types. In [34], we investigated the impact of various sources of variability on the NCFET transistor compared to the baseline transistor. In addition, the impact of variability effects on the delay of all standard cells is also studied for both baseline and NCFET cells.…”

Section: Ncfet Reliability Discussionmentioning

confidence: 99%

Impact of NCFET on Neural Network Accelerators

et al. 2021

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This is the first work to investigate the impact that Negative Capacitance Field-Effect Transistor (NCFET) brings on the efficiency and accuracy of future Neural Networks (NN). NCFET is at the forefront of emerging technologies, especially after it has become compatible with the existing fabrication process of CMOS. Neural Network inference accelerators are becoming ubiquitous in modern SoCs and there is an ever-increasing demand for tighter and tighter throughput constraints and lower energy consumption. To explore the benefits that NCFET brings to NN inference regarding frequency, energy, and accuracy, we investigate different configurations of the multiply-add (MADD) circuit, which is the core computational unit in any NN accelerator. We demonstrate that, compared to the baseline 7nm FinFET technology, its negative capacitance counterpart reduces the energy by 55%, without any frequency reduction. In addition, it enables leveraging higher computational precision, which results to a considerable improvement in the inference accuracy. Importantly, the achieved accuracy improvement comes also together with a significant energy reduction and without any loss in frequency.

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Section: Ncfet Reliability Discussionmentioning

confidence: 99%

Impact of NCFET on Neural Network Accelerators

et al. 2021

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“…The simulation also shows that ∆T C (SHE) decreases with V dd decreases and reaches ≈50 • C at 0.5V for 3-fins and ≈120 • C for 7-fins. Please note that this high temperature is enclosed within transistor's channel while the chip temperature is still relatively cool and that silicon can cope with these temperatures [30] and suffer only from electrical degradations. reliability issues [13]…”

Section: Impact Of Self Heating On Transistorsmentioning

confidence: 99%

“…To demonstrate such variation, we simulate 1000 different nFinFET and 1000 different pFinFET transistors (i.e., different length, width, etc) using HSPICE. The actual variability data are taken from [30], [31] for Intel 14nm FinFET technology. We study the variations for T C high and low for a large range of voltages [0.2V-0.7V] with 10mV steps (see Algorithm 1).…”

Section: Appendix B Ztc Of Transistors Under Process Variationsmentioning

confidence: 99%

Minimizing Excess Timing Guard Banding Under Transistor Self-Heating Through Biasing at Zero-Temperature Coefficient

et al. 2021

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Self-Heating Effects (SHE) is known as one of the key reliability challenges in FinFET and beyond. Large timing guardbands are necessary, which we try to reduce. In this work, we propose operating (biasing) processors at Zero-Temperature Coefficient (ZTC) to contain (mitigate) SHE-induced delay. Operating at ZTC allows near-zero timing guard band to protect circuits against SHE. However, a trade-off is found between thermal timing guardband and performance loss from lowering the voltage.

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“…One of the main process challenges is the integration of ferroelectric material in the gate stack with a high quality interface with the silicon. An inflection point occurred in 2012, after the discovery of ferroelectricity in HfO 2 based materials, which made the NCFET technology compatible with the standard CMOS technology process [20]- [22]. Subsequently, several experimental works have demonstrated NCFETs with HfO 2 [19] and steep sub-threshold slope, NC-FinFET shows an increased complexity in its behavior compared to conventional FinFET.…”

Section: B Negative Capacitance Finfetmentioning

confidence: 99%

“…A compact model [6] based on BSIM-CMG is used for emerging NC-FinFET. Details on the used NC-FinFET modeling and FinFET device calibration with industrial measurements are available in [20] and [21], respectively.…”

Section: A Experimental Setupmentioning

confidence: 99%