Impact of strained channel on electrical properties of Junctionless Double Gate MOSFET

Abstract

Application of strained channel in Metal-oxide-semiconductor Field Effect Transistors (MOSFET) technology influences the electrical properties due to the significant changes in the energy band structure of silicon lattices. Thus, in this paper, a comprehensive analysis is conducted to investigate the impact of strained channel towards several electrical properties of junctionless double-gate MOSFET. The comparative analysis is carried out by simulating two different sets of device structure which are JLDGM device (without strain) and junctionless double-gate strained MOSFET (JLDGSM) device. The results show that the strained channel has improved the on-state current (ION), on-off ratio, transconductance (gm) and transconductance generation factor (TGF) by approximately 58 %, 98%, 98%, and 44% respectively. The significant improvement is mainly attributed to the presence of biaxial strain boosting the electron mobility in the channel. The intrinsic gate delay (τint) has significantly reduced by approximately 52% as the strained channel is applied. Since the variation of intrinsic gate capacitances (Cint) is very minimal (4%) as the strained channel is applied, the gate delay is dominantly governed by the drain current. However, the application of strain channel has increased the dynamic power dissipation (Pdyn) for approximately 19% mainly due to slightly increased intrinsic gate capacitances.

Work function variations on electrostatic and RF performances of JLSDGM Device

“…The results have showed excellent device properties where both I ON and g m (max) were estimated at 1680 µA/µm and 2.79 mS/µm respectively. Another published work emphasized on the impact of strain channel on n-JLSDGM properties [25]. The results reveal the adoption of strain effect has tremendously enhanced the channel mobility, on-state current, on-off ratio and transconductance of the device.…”

“…It has been proven to provide a significant boost in the transistor's electrostatic and radio frequency (RF) performance by integrating silicon-germanium (SiGe) on silicon layer (strained channel), while keeping the compatibility with complementary metal oxide semiconductor (CMOS) technology [23]. The placement of HKMG layers on the top of the strained channel could further enhance the carriers mobility while maintaining acceptable leakage current (I OFF ) [24], [25] have emphasized that strainengineered SiGe-based channel improved the transistor performance but the variability impact on ultra-scale nanowire resulting in strong V th variations should be seriously looked into [26].…”

Evolution of type-II hetero-strain cylindrical-gate-all-around nanowire FET for exploration and analysis of enriched performances

“…Numerous approaches, including mobility enhanmcent using strain technologgy 3 , high-k dielectrics metal gate 4 , optimal doping profile design 5 , quasi-ballistic FETs 6 , and Nanowire (NW) FETs 7 , are researched in order to boost transistor performance and lower device variability. According to the literature, global strain and local strain generates biaxial and uniaxial strain, respectively 8 , bringing about designs such as: strain-silicon on relaxed SiGe 9 , dual-layer strained channel (s-Si/s-SiGe) 10 , Strain-silicon on insulator (SSOI) 11 , and Hetero-structure on insulator (HOI) 12 . In order to bridge the energy band gap for improved electron mobility, silicon is subjected to increased strain, which lowers the threshold voltage (V th ) 10 .…”

“…According to the literature, global strain and local strain generates biaxial and uniaxial strain, respectively 8 , bringing about designs such as: strain-silicon on relaxed SiGe 9 , dual-layer strained channel (s-Si/s-SiGe) 10 , Strain-silicon on insulator (SSOI) 11 , and Hetero-structure on insulator (HOI) 12 . In order to bridge the energy band gap for improved electron mobility, silicon is subjected to increased strain, which lowers the threshold voltage (V th ) 10 . It is well-known that the strain strategies have no long-term reliability impact and barely affect the gate oxide quality 13 .…”