Impact of strain on hole mobility in the inversion layer of PMOS device with SiGe alloy thin film

Cheng, Shuying; Chen, K.-T.; Chang, Shu−Tong

doi:10.1016/j.tsf.2015.01.047

Cited by 4 publications

(3 citation statements)

References 24 publications

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“…The surface roughness is one of the most important factors for the carrier mobility, especially in the case of surface-channel devices. 24) It is recognized that smooth surfaces on heterostructures grown on the (110) surface are hard to obtain. [25][26][27] In, 22) we showed that surface roughness is significantly dependent on the growth method.…”

Section: Resultsmentioning

confidence: 99%

Hole mobility enhancement observed in (110)-oriented strained Si

Arimoto¹,

Utsuyama²,

Mitsui³

et al. 2020

Jpn. J. Appl. Phys.

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The development of high mobility semiconductors is required to further improve the performance of electronic devices. In this study, we report that an effective hole mobility as high as 480 cm2 V−1 s−1 has been realized in a strained Si/SiGe heterostructure pMOSFET fabricated on a (110)-oriented conventional Si wafer. This result shows the feasibility of a cost-effective Si-wafer-based semiconductor platform suitable for the next generation of integrated circuits.

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Section: Resultsmentioning

confidence: 99%

Hole mobility enhancement observed in (110)-oriented strained Si

Arimoto¹,

Utsuyama²,

Mitsui³

et al. 2020

Jpn. J. Appl. Phys.

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“…1(b)]. [36][37][38] The experimental MOSFETs had channel length L = 64 nm and channel width W = 10 μm, and equivalent oxide thickness of ∼1.6 nm as estimated using C-V measurement. 39) To investigate the BTI degradation characteristics, V g,str was applied to the gate at 125 °C while the drain, source, substrate were grounded.…”

Section: Experimental Methodsmentioning

confidence: 99%

Characterization of fast relaxation by oxide-trapped charges under BTI stress on 64 nm HfSiON/SiO₂ MOSFETs

Kim¹,

Roh²,

Kang³

2020

Jpn. J. Appl. Phys.

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For HfSiON/SiO 2 n-type and p-type MOSFETs with a channel length L = 64 nm, the fast relaxation effect of oxide-trapped charges Q ox during interrupt for bias temperature instability (BTI) degradation measurement were investigated, and a model that compensated for this effect to predict lifetime t L was proposed. Experimental results show that the fast relaxation of Q ox during threshold-voltage V th measurement rapidly saturates within 1 s and is exponentially increasing for gate stress voltage V g,str and exponentially decreasing for measurement duration t m but does not affect the BTI degradation mechanism. Using the V g,str and t m dependence of Q ox 's fast relaxation under BTI stress, t L prediction model was proposed to compensate the recovery effect by V th measurement from BTI degradation measured in slow measurement (SM) condition with t m > 1 μs. The proposed model increases the precision of the estimate of t L by considering the recovery effect of Q ox even in SM.

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“…The stabilised amount of stress and major challenges based on the epitaxial SiC source/drain of FinFET are cautiously deliberated [13] . Among the various reliability issues, positive bias temperature instability (PBTI) is the major issue which was described by the many authors for various alloy based devices such as In x Ga 1−x As FinFET [14] . But it has not been analysed for SiC FinFET, so we introduce reliability issues and their solutions for Si 1−y C y FinFET for the first time.…”

Section: Introductionmentioning

confidence: 99%

Impact of varying carbon concentration in SiC S/D asymmetric dual-k spacer for high performance and reliable FinFET

et al. 2018

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We propose a reliable asymmetric dual-k spacer with SiC source/drain (S/D) pocket as a stressor for a Si channel. This enhances the device performance in terms of electron mobility (eMobility), current driving capabilities, transconductance (Gm) and subthreshold slope (SS). The improved performance is an amalgamation of longitudinal tensile stress along the channel and reduced series resistance. We analysed the variation in drive current for different values of carbon (C) mole fraction y in Si1−yCy. It is found that the mole fraction also helps to improve device lifetime, performance enhancement also pointed by transconductance variation with the gate length. All the simulations are performed in the 3-D Sentaurus TCAD tool. The proposed device structure achieved ION = 2.17 mA/μm for Si0.3C0.7 and found that Si0.5C0.5 is more suitable for the perspective of a process variation effect for 14 nm as the gate length. We introduce reliability issues and their solutions for Si1−yCy FinFET for the first time.

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Impact of strain on hole mobility in the inversion layer of PMOS device with SiGe alloy thin film

Cited by 4 publications

References 24 publications

Hole mobility enhancement observed in (110)-oriented strained Si

Hole mobility enhancement observed in (110)-oriented strained Si

Characterization of fast relaxation by oxide-trapped charges under BTI stress on 64 nm HfSiON/SiO₂ MOSFETs

Impact of varying carbon concentration in SiC S/D asymmetric dual-k spacer for high performance and reliable FinFET

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Impact of strain on hole mobility in the inversion layer of PMOS device with SiGe alloy thin film

Cited by 4 publications

References 24 publications

Hole mobility enhancement observed in (110)-oriented strained Si

Hole mobility enhancement observed in (110)-oriented strained Si

Characterization of fast relaxation by oxide-trapped charges under BTI stress on 64 nm HfSiON/SiO2 MOSFETs

Impact of varying carbon concentration in SiC S/D asymmetric dual-k spacer for high performance and reliable FinFET

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Characterization of fast relaxation by oxide-trapped charges under BTI stress on 64 nm HfSiON/SiO₂ MOSFETs