Impact of self-heating effect on the performance of hybrid FinFET

Nelapati, Rajeev Pankaj; Sivasankaran, K.

doi:10.1016/j.mejo.2018.04.015

Cited by 16 publications

(8 citation statements)

References 19 publications

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“…Comparison of the obtained results of temperature distribution along and across the channel with the results of investigation of the self-heating effect in an inverse-mode FinFET [10] leads to the conclusion that the observed differences in the temperature distribution are related not so much to the presence or lack of drainage and source areas as to the location and size of the contacts to these areas. These contacts contribute to significant heat dissipation and affect the temperature distribution along the channel of the transistor.…”

mentioning

confidence: 77%

“…This results in different dissipation of heat along the entire silicon channel and the corresponding temperature distribution. The temperatures in the middle and the ends of the transistors differ by 1−2 K. These temperature changes are small, but estimations the data reported in [10] show that, in the above-threshold region, for each 1 μm of channel width, changes in the drain current are of the order of 0.1 μA with a temperature change of 1 K. This can be important when using transistors in circuits with low power consumption. The side faces of the vertically lower part of the channel has contact with a back oxide layer, which has a thermal conductivity in the range of from 7 to 13 W/(mK).…”

mentioning

confidence: 89%

“…An increase in the temperature in the channel (the effect of self-heating) leads to a decrease in the drain current and a corresponding degradation of transistor performance. The self-heating effect and its dependence on the configuration and the sizes of different layers have been fairly well studied in the inverse mode FinFETs [9,10]. However, in junctionless vertical MOS transistors operating in accumulation mode, this effect has been studied very few.…”

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confidence: 99%

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The Self-Heating Effect in Junctionless Fin Field-Effect Transistors Based on Silicon-on-Insulator Structures with Different Channel Shapes

et al. 2021

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The self-heating effect is simulated in a nanoscale junctionless fin field-effect transistor fabricated on the basis of silicon-on-insulator structures with a transistor base cross section of a rectangular, trapezoidal, or triangular shape. It is shown that, for the structures under consideration, the temperature in the middle of the transistor is lower than along its lateral edges near the source and drain.

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confidence: 77%

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confidence: 89%

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confidence: 99%

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The Self-Heating Effect in Junctionless Fin Field-Effect Transistors Based on Silicon-on-Insulator Structures with Different Channel Shapes

et al. 2021

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“…FinFET has well established structure and fabrication due to this TSMC and Intel manufacturing Industries made used from 2011 to till date at sub 22nm technology nodes [5]. SOI FinFET shows reduced device cross talk, lower junction leakage, fully dielectric isolation, lower junction leakage, reduced capacitance, nearly ideal subthreshold slope [6][7][8]. FinFET reduces short channel effects by wrapping gate over channel from four sides.…”

Section: Introductionmentioning

confidence: 99%

Reliability and Power Analysis of FinFET Based SRAM

Navaneetha¹,

Bikshalu

2021

Silicon

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Demand for accommodating more and new functionalities within a single chip such as SOC needs a novel devices and architecture such as FinFET device instead of MOSFET. FinFET is emerged as nonplanar, multigate device to overcome short channel effects such as subthreshold swing deterioration, drain induced barrier lowering, threshold voltage roll off which degrade circuit performance. As the need of device technology is mounting in electronic gadgets the important parameters are taken into consideration such as low leakage, high reliability, low power dissipation, and high operating speed.Reliability is one of key considerations in converting a proof of concept into reality. In this work Reliability of FinFET device is studied experimentally according to ITRS (international technology roadmap for semiconductor) roadmap using several standard test protocols such as multiple current stressing, harsher environment conditions, and effect of electromigration. Furthermore, power analysis of FinFET based SRAM is done by using 7nm bsimcmg PTM les in mentor graphics tool. The FinFET based SRAM shown low leakage, power dissipation, delay compared to existing conventional MOSFET based SRAM.

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“…Zhang et al proposed hybrid FinFET [5] and was later explored by Fahad et al in [6]. Subsequently, the impact of high-k symmetric and asymmetric spacer, fin shape, and temperature on the performance of the hybrid FinFETs were analyzed by Pradhan et al [7,8,9,10]; and the effect of self-heating on the performance of hybrid FinFETs was studied by Nelapati et al [11].…”

Section: Introductionmentioning

confidence: 99%

Design and Performance Analysis of Hybrid SELBOX Junctionless FinFET

Nelapati

Sivasankaran²

2019

Informacije MIDEM

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In this work, the performance of selective buried oxide junction-less (SELBOX-JL) transistor at a FinFET structure is analysed using numerical simulations. The proposed structure exhibits better thermal resistance (R TH ), which is the measure of the self-heating effect (SHE). The DC and analog performances of the proposed structure were studied and compared with the conventional and hybrid (or inverted-T) JLFinFETs (JLTs). The I ON of the hybrid SELBOX-JLFinFET is 1.43x times better than the ION of the JLT due to the added advantage of different technologies, such as 2D-ultra-thin-body (UTB), 3D-FinFET, and SELBOX. The proposed device is modeled using sprocess and simulation study is carried using sdevice. Various analog parameters, such as transconductance (g m ), transconductance generation factor (TGF = g m /I DS ), unity current gain frequency (f T ), early voltage (V EA ), total gate capacitance (C gg ), and intrinsic gain (A 0 ), are evaluated. The proposed device with a minimum feature size of 10nm exhibited better TGF, f T , V EA , and A 0 in the deep-inversion region of operation. Analiza zasnove in učinkovitosti hibridnega brezspojnega SELBOX FinFET-aIzvleček: V članku je analiziran brezspojni SELBOX-JL transistor v FinFET strukturi. Predlagana struktura izkazuje boljšo termično upornost, ki je merjena preko lastnega segrevanja. DC in analogne lastnosti predlagan strukture so primerjanes konvencionalnimi in hibridnimi strukturami. Tok hibridnega SELBOX-JLFinFET je 1.43-krat boljši kot pri JLT zaradi uporabe drugačne tehnologije, kot je 2D ultra tanko ohišje, 3D-FinFET in SELBOX. Ocenjeni so številni parametri, kot je transkonduktanca, generacijski faktor transkonduktance, frekvenca tokovnega ojačenja, zgodnja napetost, skupna kapacitivnost vrat in osnovno ojačenje.Ključne besede: Brezspojni FinFET, hibridni SELBOX-JLFinFET, lastno segrevanje, f T , TGF.

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Impact of self-heating effect on the performance of hybrid FinFET

Cited by 16 publications

References 19 publications

The Self-Heating Effect in Junctionless Fin Field-Effect Transistors Based on Silicon-on-Insulator Structures with Different Channel Shapes

The Self-Heating Effect in Junctionless Fin Field-Effect Transistors Based on Silicon-on-Insulator Structures with Different Channel Shapes

Reliability and Power Analysis of FinFET Based SRAM

Design and Performance Analysis of Hybrid SELBOX Junctionless FinFET

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