Impact of self-heating and thermal coupling on analog circuits in SOI CMOS

Tenbroek, B.M.; Lee, M.S.L.; Redman-White, W.; Bunyan, R.J.T.; Uren, Michael J.

doi:10.1109/4.701253

Cited by 65 publications

(32 citation statements)

References 16 publications

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“…As the current saturation is an important metric which determines the transistor gain, a better understanding of velocity saturation and the role of the substrate is needed to advance the development of graphene-based electronics. As in the case of other materials and devices, 24,25 high current in graphene-based devices leads to lattice heating, 26 which must also be considered in realistic models.…”

Section: Introductionmentioning

confidence: 99%

Theoretical analysis of high-field transport in graphene on a substrate

Serov

Ong

Fischetti

et al. 2014

Journal of Applied Physics

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We investigate transport in graphene supported on various dielectrics (SiO2, BN, Al2O3, HfO2) through a hydrodynamic model which includes self-heating and thermal coupling to the substrate, scattering with ionized impurities, graphene phonons and dynamically screened interfacial plasmonphonon (IPP) modes. We uncover that while low-field transport is largely determined by impurity scattering, high-field transport is defined by scattering with dielectric-induced IPP modes, and a smaller contribution of graphene intrinsic phonons. We also find that lattice heating can lead to negative differential drift velocity (with respect to the electric field), which can be controlled by changing the underlying dielectric thermal properties or thickness. Graphene on BN exhibits the largest highfield drift velocity, while graphene on HfO2 has the lowest one due to strong influence of IPP modes.

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Section: Introductionmentioning

confidence: 99%

Theoretical analysis of high-field transport in graphene on a substrate

Serov

Ong

Fischetti

et al. 2014

Journal of Applied Physics

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“…In order to explore the way in which they incorporate together, the small-signal equivalent circuit method in [17] is used. With this method, a MOS device equals to the circuit in Fig.3.…”

Section: Combination Mismatch Effectmentioning

confidence: 99%

Symmetry constraint based on mismatch analysis for analog layout in SOI technology

Liu¹,

Dong²,

Hong³

et al. 2008

2008 Asia and South Pacific Design Automation Conference

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-The conventional tools for mismatch elimination such as geometric symmetry and common centroid technology can only eliminate systematic mismatch, but can do little to reduce random mismatch and thermal-induced mismatch. As the development of VLSI technology, the random mismatch is becoming more and more serious. And in the context of Silicon on Insulator (SOI), the self-heating effect leads to unbearable thermal-induced mismatch. Therefore, in this paper, we first propose a new model which can estimate the combination effect of both random mismatch and thermal-induced mismatch by mismatch analysis and SPICE simulation. And in order to meet the different sensitivities of different symmetry pairs, an automatic classification tool and a configurable optimization process are also introduced. All of these are embedded in the floorplanning process. The final experimental results prove the effectiveness of our method.

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“…The model has been used extensively, both for investigations into physical behavior [14], and for full chip designs, including continuous-time filters and switched-capacitor A/D converters [42]. Some of the important capabilities of the model are highlighted here, using simulations and measurements of small circuit cells.…”

Section: B Circuit Simulationsmentioning

confidence: 99%

“…Analog circuits, however, can be significantly affected. Output conductances can be low or even negative at low frequencies and then rise with frequency [13], leading to unforeseen gain and phase 0018-9200/01$10.00 © 2001 IEEE variations [14]. Matching can also be disturbed by heat flow from adjacent devices [14].…”

Section: Introductionmentioning

confidence: 99%

A physically based compact model of partially depleted SOI MOSFETs for analog circuit simulation

Lee

Tenbroek

Redman-White

et al. 2001

IEEE J. Solid-State Circuits

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Abstract-In this paper, the Southampton Thermal AnaloGue (STAG) compact model for partially depleted (PD) silicon-on-insulator (SOI) MOSFETs is presented. The model uses a single expression to model the channel current, thereby ensuring continuous transition between all operating regions. Furthermore, care has been taken to ensure that this expression is also infinitely differentiable, resulting in smooth and continuous conductances and capacitances as well as higher order derivatives. Floating-body effects, which are particular to PD SOI and which are of concern to analog circuit designers in this technology, are well modeled. Small geometry effects such as channel length modulation (CLM), drain-induced barrier lowering (DIBL), charge sharing, and high field mobility effects have also been included.Self-heating (SH) effects are much more apparent in SOI devices than in equivalent bulk devices. These have been modeled in a consistent manner, and the implementation in SPICE3f5 gives the user an additional thermal node which allows internal device temperature rises to be monitored and also accommodates the modeling of coupled heating between separate devices. The model has been successfully used to simulate a variety of circuits which commonly cause problems with convergence. Due to its inherent robustness, the model can normally achieve convergence without recourse to the setting of initial nodal voltage estimates.

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Impact of self-heating and thermal coupling on analog circuits in SOI CMOS

Cited by 65 publications

References 16 publications

Theoretical analysis of high-field transport in graphene on a substrate

Theoretical analysis of high-field transport in graphene on a substrate

Symmetry constraint based on mismatch analysis for analog layout in SOI technology

A physically based compact model of partially depleted SOI MOSFETs for analog circuit simulation

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