Molybdenum disulfide is considered as one of the most promising two-dimensional semiconductors for electronic and optoelectronic device applications. So far, the charge transport in monolayer molybdenum disulfide is dominated by extrinsic factors such as charged impurities, structural defects and traps, leading to much lower mobility than the intrinsic limit. Here we develop a facile low-temperature thiol chemistry route to repair the sulfur vacancies and improve the interface, resulting in significant reduction of the charged impurities and traps. High mobility 480 cm 2 V À 1 s À 1 is achieved in backgated monolayer molybdenum disulfide field-effect transistors at room temperature. Furthermore, we develop a theoretical model to quantitatively extract the key microscopic quantities that control the transistor performances, including the density of charged impurities, short-range defects and traps. Our combined experimental and theoretical study provides a clear path towards intrinsic charge transport in two-dimensional dichalcogenides for future high-performance device applications.

Heat flow in nanomaterials is an important area of study, with both fundamental and technological implications. However, little is known about heat flow in two-dimensional devices or interconnects with dimensions comparable to the phonon mean free path. Here we find that short, quarter-micron graphene samples reach B35% of the ballistic thermal conductance limit up to room temperature, enabled by the relatively large phonon mean free path (B100 nm) in substrate-supported graphene. In contrast, patterning similar samples into nanoribbons leads to a diffusive heat-flow regime that is controlled by ribbon width and edge disorder. In the edge-controlled regime, the graphene nanoribbon thermal conductivity scales with width approximately as BW 1.8±0.3 , being about 100 W m À 1 K À 1 in 65-nm-wide graphene nanoribbons, at room temperature. These results show how manipulation of two-dimensional device dimensions and edges can be used to achieve full control of their heat-carrying properties, approaching fundamentally limited upper or lower bounds.

We directly image hot spot formation in functioning mono- and bilayer graphene field effect transistors (GFETs) using infrared thermal microscopy. Correlating with an electrical-thermal transport model provides insight into carrier distributions, fields, and GFET power dissipation. The hot spot corresponds to the location of minimum charge density along the GFET; by changing the applied bias, this can be shifted between electrodes or held in the middle of the channel in ambipolar transport. Interestingly, the hot spot shape bears the imprint of the density of states in mono- vs bilayer graphene. More broadly, we find that thermal imaging combined with self-consistent simulation provide a noninvasive approach for more deeply examining transport and energy dissipation in nanoscale devices.

Transition-metal dichalcogenides (TMDCs) are important class of two-dimensional (2D) layered materials for electronic and optoelectronic applications, due to their ultimate body thickness, sizable and tunable bandgap, and decent theoretical room-temperature mobility of hundreds to thousands cm 2 /Vs. So far, however, all TMDCs show much lower mobility experimentally because of the collective effects by foreign impurities, which has become one of the most important limitations for their device applications. Here, taking MoS2 as an example, we review the key factors that bring down the mobility in TMDC transistors, including phonons, 2 charged impurities, defects, and charge traps. We introduce a theoretical model that quantitatively captures the scaling of mobility with temperature, carrier density and thickness. By fitting the available mobility data from literature over the past few years, we are able to obtain the density of impurities and traps for a wide range of transistor structures. We show that interface engineering such as oxide surface passivation, high-k dielectrics and BN encapsulation could effectively reduce the impurities, leading to improved device performances. For few-layer TMDCs, we analytically model the lopsided carrier distribution to elucidate the experimental increase of mobility with the number of layers. From our analysis, it is clear that the charge transport in TMDC samples is a very complex problem that must be handled carefully.We hope that this Review can provide new insights and serve as a starting point for further improving the performance of TMDC transistors.3

We examine thermal transport in graphene supported on SiO 2 using molecular dynamics (MD) simulations. Coupling to the substrate reduces the thermal conductivity (TC) of supported graphene by an order of magnitude, due to damping of the flexural acoustic (ZA) phonons. However, increasing the strength of the graphene-substrate interaction enhances the TC of supported graphene, contrary to expectations. The enhancement is due to the coupling of graphene ZA modes to the substrate Rayleigh waves, which linearizes the dispersion and increases the group velocity of the hybridized modes. These findings suggest that the TC of 2-D supported graphene is tunable through surface interactions, providing a novel possibility for controlled energy flow in nanomaterials.

Research into the physical properties of MoS 2 and other semiconducting transition metal dichalcogenides [1] (TMDs) has increased considerably in recent years, owing to their potential applications in post-CMOS electronics [2][3][4] , optoelectronics [5][6][7] and valleytronics [8][9][10] . Some of the properties of monolayer MoS 2 that are advantageous for electronic applications include a direct band gap of 1.8 eV [11,12] as well as a film thickness of less than 1 nm which gives superior electrostatic control of the charge density and current even at the transistor scaling limit [3,13] . In spite of these favorable properties, the widely reported low electron mobility in monolayer MoS 2 poses a serious obstacle to its integration into post-CMOS nanoelectronics. The nature of charge transport in MoS 2 , especially at room temperature, remains poorly understood despite considerable amount of theoretical and experimental researches.For example, the theoretically predicted intrinsic phonon-limited mobility at room temperature is in the range of 200-410 cm 2 /Vs [14.15] while most experimentally reported values are much smaller [16][17][18][19][20][21][22][23] . Before any semiconducting material can become useful for potential nanoelectronic device applications, a critical assessment of its intrinsic charge transport properties at room temperature is needed, requiring the realization of high-quality samples with carrier mobility in the phonon-limited regime.The phonon-limited transport regime was demonstrated for graphene [24] and carbon nanotubes [25] . However, despite many recent efforts to improve carrier mobility by means of topgate [17] , chemical functionalization [21] and BN gate dielectrics [22] , phonon-limited transport regime has not been explicitly demonstrated in monolayer TMDs including MoS 2 .The possible reasons for the discrepancy between the theoretical upper limit and experimental data include Coulomb impurities (CI), traps and defects in low-quality samples [19][20][21][22][23] . These extrinsic sources of scattering have so far precluded any rigorous examination of the intrinsic scattering mechanisms that affect electron mobility. A particularly important source of scattering is from CI at the semiconductor-dielectric interface, which is believed to be the most important limiting factor in current MoS 2 devices [26] . Recently, it has been demonstrated that by sandwiching the monolayer MoS 2 channel between BN layers, CI scattering can be significantly suppressed, leading to a record-high mobility of over 1000 cm 2 /Vs at low temperatures [22][23] . The technologically relevant room-temperature mobility, however, still lags the best devices on SiO 2 for reasons not well understood. Nonetheless, significant recent progress in reducing the deleterious effects of CI, traps and defects on the mobility [20][21][22][23] begin to set the stage for the realization of room-temperature charge transport in the phonon-limited regime.It has been shown experimentally that the deposition of a high-κ top ...

Using first-principles calculations and non-equilibrium Green's function method, we investigate the ballistic thermal transport in single-layer phosphorene. A significant crystallographic orientation dependence of thermal conductance is observed, with room temperature thermal conductance along zigzag direction being 40% higher than that along armchair direction. Furthermore, we find that the thermal conductance anisotropy with the orientation can be tuned by applying strain. In particular, the zigzag-oriented thermal conductance is enhanced when a zigzag-oriented strain is applied but decreases when an armchair-oriented strain is applied; whereas the armchair-oriented thermal conductance always decreases when either a zigzag-or an armchair-oriented strain is applied. The present work suggests that the remarkable thermal transport anisotropy and its strain-modulated effect in single-layer phosphorene may be used for thermal management in phosphorene-based electronics and optoelectronic devices.

We investigate thermal energy coupling between carbon nanotubes (CNTs) and SiO 2 with nonequilibrium molecular dynamics simulations. The phonon thermal boundary conductance (g) per unit length is found to scale proportionally with the strength of the Van der Waals interaction (~χ), with CNT diameter (~D), and as power law of temperature (~T 1/3 between 200-600 K). The thermal relaxation time of a single CNT on SiO 2 is independent of diameter, τ ≈ 85 ps. With the standard set of parameters g ≈ 0.1 WK -1 m -1 for a 1.7 nm diameter CNT at room temperature. Our results are comparable to, and explain the range of experimental values for CNT-SiO 2 thermal coupling from variations in diameter, temperature, or details of the surface interaction strength.