Impact of run-time reconfiguration on design and speed - A case study based on a grid of run-time reconfigurable modules inside a FPGA

Strunk, Jochen; Volkmer, Toni; Stephan, Klaus; Rehm, Wolfgang; Schick, H.

doi:10.1109/ipdps.2009.5161221

Cited by 4 publications

(4 citation statements)

References 4 publications

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“…The impact on the design and the speed of a grid of RTRMs connected in a star network topology as network on chip has been investigated in [3]. The ReCoBus [6] architecture does not support two dimensional grids and furthermore would result in low operating frequencies connecting all modules in-line.…”

Section: Synchronously Clocked Rtr Gridsmentioning

confidence: 99%

“…Such a grid of RTRMs, e.g. presented in [3], allows compute kernels or special purpose processing engines to be executed on demand. Multi context creation of the same module is also feasible, when supported by the on-chip communication network and the supporting framework.…”

Section: Introductionmentioning

confidence: 99%

“…[3], imposes the restriction that the on-chip network or central controller and the RTRMs must be driven by one and the same clock only. Achieving maximum computing performance would imply that the maximum clock speed of all participating RTRMs, realizing different tasks within the grid, have the same peak clock speed performance as the onchip communication network.…”

Section: Introductionmentioning

confidence: 99%

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Design and Performance of a Grid of Asynchronously Clocked Run-Time Reconfigurable Modules on a FPGA

Strunk

Volkmer

Rehm

et al. 2009

2009 International Conference on Reconfigurable Computing and FPGAs

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This paper examines the feasibility of utilizing a grid of asynchronously clocked run-time reconfigurable modules (RTRMs) on a dynamically and partially reconfigurable (DPR) FPGA. In contrast to a synchronously clocked grid studied in research, the design, the implementation, the performance and the resource utilization of an asynchronously clocked grid is shown. Such a run-time reconfigurable (RTR) grid on a FPGA can be utilized to dynamically offload compute functions on a host coupled system, providing multi-user and multi-context execution on behalf of user demands. For embedded systems it can be utilized as a highly dynamical platform by providing functional enhancement by module replacement during run-time. The presented platform leverages synthesis and development constraints and is able to increase the overall throughput by allowing multiple clock domains within the grid. The performance and the additional resource utilization of handling multiple clock domains is compared to synchronously clocked grids. As proof of concept a case study with a grid of 47 RTRMs is conducted on state of the art Virtex-5 FPGAs.

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Section: Synchronously Clocked Rtr Gridsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Design and Performance of a Grid of Asynchronously Clocked Run-Time Reconfigurable Modules on a FPGA

Strunk

Volkmer

Rehm

et al. 2009

2009 International Conference on Reconfigurable Computing and FPGAs

Self Cite

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show abstract

“…We need to consider the following important factors. Firstly, the FPGA supports a technique called Partial Dynamic Reconfiguration (PDR) [4], which allows the FPGA to reconfigure some logic blocks at runtime without affecting the rest of the logic blocks [5]. This technology can dynamically replace the internal logic functions of the FPGA, which greatly increases system flexibility and resource utilization.…”

Section: Introductionmentioning

confidence: 99%

Resource-Aware Task Scheduling and Placement in Multi-FPGA System

Sun

Zhang

2019

IEEE Access

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With the development of high performance computing, Field Programmable Gate Arrays (FPGAs) are widely used for task acceleration. Partial reconfigurable technology provides the possibility of multi-task concurrent computation on FPGAs. However, it is still difficult to achieve high performance multi-task acceleration in multi-FPGA systems due to the resource contention in limited hardware resources and reconfiguration overhead. In this paper, we propose a two-stage task scheduling approach in multi-FPGA systems to optimize task execution efficiency. At the first scheduling stage, we select an appropriate computing unit for each task considering the subtask similarity and resource requirement similarity to reduce the possibility of reconfiguration and resource contention. At the second scheduling stage, we coordinate the subtask scheduling and placement to make full use of the hardware resources of FPGAs and improve the acceleration performance. Experiments show that our two-stage scheduling approach significantly reduces the tasks makespan and improves the utilization of resources compared with other traditional methods. INDEX TERMS Multi-FPGA, task scheduling, task placement, partial reconfiguration.

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Adaptive hardware context-switching approach for reconfigurable systems

Lee

Tseng

2010

2nd Asia Symposium on Quality Electronic Design (ASQED)

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Impact of run-time reconfiguration on design and speed - A case study based on a grid of run-time reconfigurable modules inside a FPGA

Cited by 4 publications

References 4 publications

Design and Performance of a Grid of Asynchronously Clocked Run-Time Reconfigurable Modules on a FPGA

Design and Performance of a Grid of Asynchronously Clocked Run-Time Reconfigurable Modules on a FPGA

Resource-Aware Task Scheduling and Placement in Multi-FPGA System

Adaptive hardware context-switching approach for reconfigurable systems

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