Impact of Read Disturb on Multilevel RRAM based Inference Engine: Experiments and Model Prediction

Shim, Wonbo; Luo, Yandong; Seo, Jae-sun; Yu, Shimeng

doi:10.1109/irps45951.2020.9129252

Cited by 30 publications

(26 citation statements)

References 21 publications

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“…Once programmed, the hardware is expected to perform inference continuously, without having to reprogram the model parameters. Unfortunately, OxRRAM cells suffer from the read disturb issue, where a cell's resistance state may drift from its programmed value upon repeated access during inference [3]. We show that resistance drifts can lead to a lower inference accuracy (see Section VI).…”

Section: Introductionmentioning

confidence: 93%

“…In OxRRAM technology, the transition from HRS to one of the LRS states is governed by a sudden decrease of the vertical filament gap on application of a stress voltage during spike propagation [3]. This is illustrated in the left subfigure of Figure 3 where the vertical filament gap is shown to reduce by an amount h. This may result in a conducting filament between the two metal layers causing the resistive state to change from HRS to LRS.…”

Section: B Read Disturbance Issues Of Oxrram Cellsmentioning

confidence: 99%

“…The transition from one of the LRS states is governed by the lateral filament growth [3]. This is illustrated in the right subfigure of Figure 3.…”

Section: B Read Disturbance Issues Of Oxrram Cellsmentioning

confidence: 99%

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On the Mitigation of Read Disturbances in Neuromorphic Inference Hardware

Paul¹,

Song²,

Titirsha³

et al. 2022

Preprint

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Non-Volatile Memory (NVM) cells are used in neuromorphic hardware to store model parameters, which are programmed as resistance states. NVMs suffer from the read disturb issue, where the programmed resistance state drifts upon repeated access of a cell during inference. We show that resistance drifts can lower the inference accuracy. To address this, it is necessary to periodically reprogram model parameters to the hardware (a high overhead operation). We study read disturb failures of an NVM cell. Our analysis show both a strong dependency on model characteristics such as synaptic activation and criticality, and on the voltage used to read resistance states during inference. We propose a system software framework to incorporate such dependencies in programming model parameters on NVM cells of a neuromorphic hardware. At the core of our framework is a convex optimization formulation which aims to implement synaptic weights that have more activations and are critical, i.e., those that have high impact on accuracy on NVM cells that are exposed to lower voltages during inference. In this way, we increase the time interval between two consecutive reprogramming of model parameters. We evaluate our system software with many emerging inference models on a neuromorphic hardware simulator and show a significant reduction in the system overhead.

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Section: Introductionmentioning

confidence: 93%

Section: B Read Disturbance Issues Of Oxrram Cellsmentioning

confidence: 99%

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On the Mitigation of Read Disturbances in Neuromorphic Inference Hardware

Paul¹,

Song²,

Titirsha³

et al. 2022

Preprint

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“…Moreover, the voltage applied to the cell should be as small as possible to avoid reading disturb issues [ 49 ]. It presents a significant challenge on BL-enhancing schemes and sensing schemes [ 68 , 69 , 70 , 71 ].…”

Section: The Design Challenges Of Rrammentioning

confidence: 99%

Sensing Circuit Design Techniques for RRAM in Advanced CMOS Technology Nodes

et al. 2021

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Resistive random access memory (RRAM) is one of the most promising new nonvolatile memories because of its excellent properties. Moreover, due to fast read speed and low work voltage, it is suitable for seldom-write frequent-read applications. However, as technology nodes shrink, RRAM faces many issues, which can significantly degrade RRAM performance. Therefore, it is necessary to optimize the sensing schemes to improve the application range of RRAM. In this paper, the issues faced by RRAM in advanced technology nodes are summarized. Then, the advantages and weaknesses in the novel design and optimization methodologies of sensing schemes are introduced in detail from three aspects, the reference schemes, sensing amplifier schemes, and bit line (BL)-enhancing schemes, according to the development of technology in especially recent years, which can be the reference for designing the sensing schemes. Moreover, the waveforms and results of each method are illustrated to make the design easy to understand. With the development of technology, the sensing schemes of RRAM become higher speed and resolution, low power consumption, and are applied at advanced technology nodes and low working voltage. Now, the most advanced nodes the RRAM applied is 14 nm node, the lowest working voltage can reach 0.32 V, and the shortest access time can be only a few nanoseconds.

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“…This multi-level approach was successfully employed in implementing a 2-layer feedforward neural network for the classification of the MNIST dataset [27,28]. Although similar studies can be found elsewhere [15,[29][30][31], none of them evaluate how the programming parameters used to define the synaptic weights in the RRAM array impact the results obtained by the VMM operations and, hence, on the accuracy of the corresponding DNN.…”

Section: Introductionmentioning

confidence: 99%

Optimization of Multi-Level Operation in RRAM Arrays for In-Memory Computing

et al. 2021

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Accomplishing multi-level programming in resistive random access memory (RRAM) arrays with truly discrete and linearly spaced conductive levels is crucial in order to implement synaptic weights in hardware-based neuromorphic systems. In this paper, we implemented this feature on 4-kbit 1T1R RRAM arrays by tuning the programming parameters of the multi-level incremental step pulse with verify algorithm (M-ISPVA). The optimized set of parameters was assessed by comparing its results with a non-optimized one. The optimized set of parameters proved to be an effective way to define non-overlapped conductive levels due to the strong reduction of the device-to-device variability as well as of the cycle-to-cycle variability, assessed by inter-levels switching tests and during 1 k reset-set cycles. In order to evaluate this improvement in real scenarios, the experimental characteristics of the RRAM devices were captured by means of a behavioral model, which was used to simulate two different neuromorphic systems: an 8 × 8 vector-matrix-multiplication (VMM) accelerator and a 4-layer feedforward neural network for MNIST database recognition. The results clearly showed that the optimization of the programming parameters improved both the precision of VMM results as well as the recognition accuracy of the neural network in about 6% compared with the use of non-optimized parameters.

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Impact of Read Disturb on Multilevel RRAM based Inference Engine: Experiments and Model Prediction

Cited by 30 publications

References 21 publications

On the Mitigation of Read Disturbances in Neuromorphic Inference Hardware

On the Mitigation of Read Disturbances in Neuromorphic Inference Hardware

Sensing Circuit Design Techniques for RRAM in Advanced CMOS Technology Nodes

Optimization of Multi-Level Operation in RRAM Arrays for In-Memory Computing

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