Impact of pattern dependency of SiGe layers grown selectively in source/drain on the performance of 22nm node pMOSFETs

Wang, Guilei; Moeen, M.; Abedin, A.; Xu, Ya‐Qiong; Luo, Jun; Guo, Yiluan; Qin, Changliang; Tang, Zhaoyun; Yin, Haizhou; Li, Junfeng; Jiang, Yan; Zhu, Huilong; Zhao, Chunjiang; Chen, Dapeng; Ye, Tianchun; Kolahdouz, Mohammadreza; Radamson, Henry H.

doi:10.1016/j.sse.2015.07.003

Cited by 13 publications

(15 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Further investigations about the effect of NiSiGe formation on the SiGe strain were performed. In Figure 9c, the SiGe peak is at the same position as in Figure 4b indicating the strain in SiGe is preserved during the Ni silicide formation process [49].…”

Section: Stress Measurements In Nano-scaled Transistorsmentioning

confidence: 68%

“…The 3D architecture was designed and manufactured for 22 nm node. SiGe The epi-layers may suffer from several problems e.g., facet formation [44,45], defects, micro/loading, non-uniform strain distribution, surface roughness and pattern dependency effect [46][47][48][49][50]. The pattern dependency happens when the density and size of the transistor vary in a chip.…”

Section: Stress Engineeringmentioning

confidence: 99%

“…This problem can be decreased by optimizing the growth parameters (high HCl partial pressure, low total pressure and high hydrogen carrier gas pressure) and by designing chip layouts where the exposed Si is uniformly distributed over the chip's area to create uniform gas consumption [50]. The epi-layers may suffer from several problems e.g., facet formation [44,45], defects, micro/loading, non-uniform strain distribution, surface roughness and pattern dependency effect [46][47][48][49][50]. The pattern dependency happens when the density and size of the transistor vary in a chip.…”

Section: Stress Engineeringmentioning

confidence: 99%

“…As an example, Figure 9a- [49]. The silicide layer has been formed on a sacrificial SiGe layer with lower Ge content (20%).…”

Section: Stress Measurements In Nano-scaled Transistorsmentioning

confidence: 99%

See 3 more Smart Citations

The Challenges of Advanced CMOS Process from 2D to 3D

Radamson

Zhang

et al. 2017

Applied Sciences

Self Cite

View full text Add to dashboard Cite

Abstract:The architecture, size and density of metal oxide field effect transistors (MOSFETs) as unit bricks in integrated circuits (ICs) have constantly changed during the past five decades. The driving force for such scientific and technological development is to reduce the production price, power consumption and faster carrier transport in the transistor channel. Therefore, many challenges and difficulties have been merged in the processing of transistors which have to be dealed and solved. This article highlights the transition from 2D planar MOSFETs to 3D fin field effective transistors (FinFETs) and then presents how the process flow faces different technological challenges. The discussions contain nano-scaled patterning and process issues related to gate and (source/drain) S/D formation as well as integration of III-V materials for high carrier mobility in channel for future FinFETs.

show abstract

Section: Stress Measurements In Nano-scaled Transistorsmentioning

confidence: 68%

Section: Stress Engineeringmentioning

confidence: 99%

Section: Stress Engineeringmentioning

confidence: 99%

“…As an example, Figure 9a- [49]. The silicide layer has been formed on a sacrificial SiGe layer with lower Ge content (20%).…”

Section: Stress Measurements In Nano-scaled Transistorsmentioning

confidence: 99%

See 2 more Smart Citations

The Challenges of Advanced CMOS Process from 2D to 3D

Radamson

Zhang

et al. 2017

Applied Sciences

Self Cite

View full text Add to dashboard Cite

show abstract

“…In order to provide a broad knowledge about the local and global pattern dependency, an example is pointed out here when the SiGe layers were grown selectively on S/D regions in transistors with 22 nm gate length [31]. Figure 7a shows a schematic of an 8-inch Si wafer containing 112 processed chips.…”

Section: Pattern Dependency Of Selective Epitaxymentioning

confidence: 99%

Selective Epitaxy of Group IV Materials for CMOS Application

Wang¹,

Radamson²,

Kolahdouz³

2018

Complementary Metal Oxide Semiconductor

Self Cite

View full text Add to dashboard Cite

As the International Technology Roadmap for Semiconductors (ITRS) demands an increase of transistor density in the chip, the size of transistors has been continuously shrunk. In this evolution of transistor structure, different strain engineering methods were introduced to induce strain in the channel region. One of the most effective methods is applying embedded SiGe as stressor material in source and drain (S/D) regions by using selective epitaxy. This chapter presents an overview of implementation, modeling, and pattern dependency of selective epitaxy for S/D application in CMOS. The focus is also on the wafer in and ex situ cleaning prior to epitaxy, integrity of gate, and selectivity mode.

show abstract

X-Ray Techniques

Radamson

2023

Lecture Notes in Nanoscale Science and Technology

View full text Add to dashboard Cite

Impact of pattern dependency of SiGe layers grown selectively in source/drain on the performance of 22nm node pMOSFETs

Cited by 13 publications

References 10 publications

The Challenges of Advanced CMOS Process from 2D to 3D

The Challenges of Advanced CMOS Process from 2D to 3D

Selective Epitaxy of Group IV Materials for CMOS Application

X-Ray Techniques

Contact Info

Product

Resources

About