Impact of negative bias temperature instability on digital circuit reliability

Reddy, V.; Krishnan, A.T.; Marshall, Andrew; Rodríguez, J. A.; Natarajan, S.; Rost, Tim; Krishnan, S.

doi:10.1016/j.microrel.2004.05.023

Cited by 101 publications

(67 citation statements)

References 15 publications

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“…Hence interface traps in p-channel devices in inversion are positively charged, leading to negative threshold voltage shifts. Negative bias stress generates donor states in the lower half of the band gap [17,18].…”

Section: Interface Traps and Oxide Chargesmentioning

confidence: 99%

“…Fig. 5 shows the threshold voltage shift from two different research groups when p-and n-MOSFETs are biased with positive and negative gate voltages [17,4]. Clearly p-MOSFETs under negative gate bias are the most severely affected.…”

Section: Nbti Recoverymentioning

confidence: 99%

“…The P-H bonds dissociate and the hydrogen on the way to the SiO 2 /Si interface ''picks up'' a hole to become H + , then reacts with the H from the SiH bond to form H 2 leaving behind a positively charged Threshold voltage shifts for p-and n-MOSFETs for positive and negative gate bias[17,4]. Possible interface trap creation by hydrogen.…”

mentioning

confidence: 99%

See 2 more Smart Citations

Negative bias temperature instability: What do we understand?

Schroder

2007

Microelectronics Reliability

334

134

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Section: Interface Traps and Oxide Chargesmentioning

confidence: 99%

Section: Nbti Recoverymentioning

confidence: 99%

See 1 more Smart Citation

Negative bias temperature instability: What do we understand?

Schroder

2007

Microelectronics Reliability

334

134

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“…the stress time power law), which will in return limit the lifetime of the circuits. It is reported that the SNM degradation increases with decreasing supply voltage [21], so the importance of NBTI on SRAM will be more significant with the scaling of the device dimensions. (%) Fig.4 The relative degradation of SNM under NBTI It is believed that the stability of SRAM can be improved by increasing the cell ratio (CR), which is the ratio of the driver transistor's (M2, M4) width/length (W/L) to the access transistor's (M1, M3) W/L [17,22].…”

Section: The Cmos Srammentioning

confidence: 99%

Impact of NBTI on the performance of 35nm CMOS digital circuits

Wang

Zwoliński

2008

2008 9th International Conference on Solid-State and Integrated-Circuit Technology

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The negative bias temperature instability (NBTI) of p-MOSFET has the greatest impact on the long term reliability of nano-scale devices and circuits. For several decades, NBTI research has been focused at the device physics level or on the characterization methodology, with little attention paid to the impact of NBTI on the performance of basic digital circuits. This paper discusses the effects of NBTI on 35nm technology CMOS inverters and SRAM. The delay degradation and power dissipation of the inverters, as well as the static noise margin degradation of the SRAM are analysed. Moreover, the effects of power supply voltage on inverters and the cell ratio on SRAM under NBTI are also discussed.

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“…Bias temperature instability (BTI) of CMOS devices is a continuing concern in modern silicon process technologies, as it results in long-term decrease of drive current, which can lead to unacceptable changes of signal path delay in microprocessors [1]. The BTI-induced change of threshold voltage of single field effect transistors (FETs) is conventionally measured using I-V curves, or it can be deduced from measuring ring oscillators, where the frequency of oscillation is an indirect measurement of the degradation of the device characteristics.…”

Section: Introductionmentioning

confidence: 99%