Impact of nanowire variability on performance and reliability of gate-all-around III-V MOSFETs

Shin, Sanghoon; Masuduzzaman, Muhammad; Gu, Jiangjiang; Wahab, Muhammad Abdul; Conrad, Nathan J.; Si, Mengwei; Ye, P. D.; Alam, Muhammad Ashraful

doi:10.1109/iedm.2013.6724582

Cited by 28 publications

(14 citation statements)

References 6 publications

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“…All noise measurements were performed at V ds = 50 mV and at V gs from −0.2 to 0.4 V and at room temperature unless otherwise specified. Positive bias temperature instability measurement confirms that V T shift <10 mV during noise measurement (maximum V gs = 0.4 V) is ensured [36], so that I s shift is negligible during noise measurement. Fig.…”

Section: Introductionmentioning

confidence: 57%

Low-Frequency Noise and Random Telegraph Noise on Near-Ballistic III-V MOSFETs

Conrad

Shin

et al. 2015

IEEE Trans. Electron Devices

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In this paper, we report the observation of random telegraph noise (RTN) in highly scaled InGaAs gate-allaround (GAA) MOSFETs fabricated by a top-down approach. RTN and low-frequency noise were systematically studied for devices with various gate dielectrics, channel lengths, and nanowire diameters. Mobility fluctuation is identified to be the source of 1/f noise. The 1/f noise was found to decrease as the channel length scaled down from 80 to 20 nm comparing with classical theory, indicating the near-ballistic transport in highly scaled InGaAs GAA MOSFET. Low-frequency noise in ballistic transistors is discussed theoretically.Index Terms-Ballistic transport, gate-all-around (GAA), InGaAs, low-frequency noise, MOSFET, random telegraph noise (RTN).

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Section: Introductionmentioning

confidence: 57%

Low-Frequency Noise and Random Telegraph Noise on Near-Ballistic III-V MOSFETs

Conrad

Shin

et al. 2015

IEEE Trans. Electron Devices

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“…Reliability studies have been performed both on planar devices [18][19][20][21][22][23][24][25] and on nanowire MOSFETs [15,16]. The PBTI and HCI measurements are done with an automated measure-stress-measure (MSM) setup at various bias conditions and room temperature.…”

Section: A Electrical Analysismentioning

confidence: 99%

“…Reliability performance of InGaAs MOSFETs have not met the criteria for massive production and unique reliability challenges on emerging III-V nanowire devices are also needed to be addressed [15][16][17][18][19][20][21][22][23][24][25]. Heat dissipation could also be a potential challenge, especially for GAA structures where the channel is surrounded by oxides and ALD-deposited gate metal, neither of which have high thermal conductivity.…”

Section: Introductionmentioning

confidence: 98%

Characterization and reliability of III-V gate-all-around MOSFETs

Shin

Conrad

et al. 2015

2015 IEEE International Reliability Physics Symposium

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InGaAs is a promising channel material for high performance CMOS logic circuits due to its large electron injection velocity. InGaAs Gate-All-Around (GAA) MOSFETs have been demonstrated; these transistors offer large drive current and excellent immunity to short channel effects (SCE). However, the characterization and reliability of InGaAs GAA MOSFETs are still challenging. In this paper, we (i) discuss the challenges and new characterization methodologies to evaluate D it , R sd and other parameters on short channel InGaAs GAA MOSFETs, (ii) discuss device characterization based on low frequency noise and RTN, (iii) image the complexity of heat dissipation by using newly developed thermoreflectance method, and (iv) review the current research on 3D InGaAs MOSFET reliability including PBTI, HCI, and gate dielectric breakdown.

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Section: Impacts Of Nbti/pbti On Utb Geoi Sram Cellsmentioning

confidence: 99%

Impacts of NBTI and PBTI on ultra-thin-body GeOI 6T SRAM cells

Fan

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper investigates the impact Positive Bias Temperature Instabilities (NBTI stability and performance of Ultra-Thin-Body SRAM cells compared with the SOI counter stress scenarios for Read and Write operati For UTB GeOI SRAM cells, PBTI dominates in RSNM, HSNM, cell Read access time, an while for UTB SOI SRAM cells, NBT degradations in RSNM, HSNM, and Timeonly slightly degrades due to NBTI/PBTI. T design and Word-Line Under-Drive (WL techniques are analyzed to compensate the sta due to NBTI/PBTI for UTB GeOI SRAM cell the nominal UTB GeOI SRAM cells with low GeOI SRAM cells with high Vth design suffe degradations and exhibit significant improvem HSNM, and comparable performance com nominal UTB SOI SRAM cells.

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Impact of nanowire variability on performance and reliability of gate-all-around III-V MOSFETs

Cited by 28 publications

References 6 publications

Low-Frequency Noise and Random Telegraph Noise on Near-Ballistic III-V MOSFETs

Low-Frequency Noise and Random Telegraph Noise on Near-Ballistic III-V MOSFETs

Characterization and reliability of III-V gate-all-around MOSFETs

Impacts of NBTI and PBTI on ultra-thin-body GeOI 6T SRAM cells

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