Impact of Multicycled Scheduling on Power-Area Tradeoffs in Behavioural Synthesis

Abstract

Abstract-Multicycling is a widely investigated technique for performance optimisation in behavioural synthesis. It allows an operation to execute over two or more control steps with the aim of increasing the performance and/or minimising the power consumption. This paper presents a new timeconstrained scheduling (TCS) algorithm that takes into account the combined influence of clock period and the multicycled functional units execution time on the quality of the schedules in terms of power and area. It is shown that it is possible to produce a set of solutions that have similar power consumptions, however differ in terms of resource requirements, yet meeting the imposed real-time constraint. Furthermore, extensive experiments on behavioural benchmarks show that the proposed approach is capable of obtaining schedules with single supply domain that have identical resource requirements and comparable power consumption to schedules obtained using multiple supply voltages, further reducing the design complexity.

Exploiting Power-Area Tradeoffs in Behavioural Synthesis through clock and operations throughput selection

“…The proposed approach starts generating a list of clock candidates using a modified version of [10], where it was shown how an appropriate choice of a clock period and functional units execution time allows the application of lower voltages, minimising the slack and leading to power savings. Three novel improvements were made to [10].…”

“…Three novel improvements were made to [10]. The first modification consisted of finding the operations throughput not only for the type of operation that has maximum power consumption in the design, but also for the type of operation that don't have maximum power consumption in the design.…”

“…The first modification consisted of finding the operations throughput not only for the type of operation that has maximum power consumption in the design, but also for the type of operation that don't have maximum power consumption in the design. This will allow exploring solutions that were not explored by the algorithm described in [10]. The second modification consists of considering only clock periods whose operations throughputs are different from those of the last clock period included in the list of possible candidates.…”

“…If there has not been a time violation the operations are scheduled into Ls and the delay, voltage and power of the operators are computed (line 8). The operations were scheduled with the low run time LMSE scheduler used in [10]. The clock period, schedule information, operations throughput, and the values of delay, voltage and power for the operators are saved in a structure.…”

“…The clock selection problem is not new in the context of HLS and has been addressed in previous research, where it has been shown the significant effect of clock choice on the design in terms of area [1], [3], performance [9], [12], and power [8], [10], [11]. From the previous work on clock selection, the most relevant to our work is [11].…”