Exploiting Power-Area Tradeoffs in Behavioural Synthesis through clock and operations throughput selection

Ochoa-Montiel, M.A.; Al-Hashimi, Bashir M.; Kollig, P.

doi:10.1109/aspdac.2007.358038

Cited by 6 publications

(3 citation statements)

References 11 publications

(29 reference statements)

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“…Area overhead when reducing power or energy exceeds 50% for some cases, and 25% on average. In [13] authors tradeoff area and power by different clock selections, but they relax the timing constraint T, producing circuits with 1.5T-3.5T.…”

Section: Related Workmentioning

confidence: 99%

Power optimization in heterogenous datapaths

Barrio

Memik

Molina

et al. 2011

2011 Design, Automation &Amp; Test in Europe

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12 -Heterogenous datapaths maximize the utilization of functional units (FUs) by customizing their widths individually through fragmentation of wide operands. In comparison, slices in large functional units in a homogenous datapath could be spending many cycles not performing actual useful work. Various fragmentation techniques demonstrated benefits in minimizing the total functional unit area. Upon a closer look at fragmentation techniques, we observe that the area savings achieved by heterogenous datapaths can be traded-off for power optimization. Our specific approach is to introduce choices for functional units with power/area trade-offs for different fragmentation and allocation choices, for reducing power consumption while satisfying the area constraint imposed on the heterogenous datapath. As low power FUs in literature produce an area penalty, a methodology must be developed in order to introduce them in the HLS flow while complying with the area constraint. We propose an allocation and module selection algorithms that pursue a trade-off between area and power consumption for fragmented datapaths under a total area constraint. Results show that it is possible to reduce power by 37% on average (49% in the best case). Moreover latency and cycle time will be equal or nearly the same as in the baseline case, which will lead to an energy reduction, too.

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Section: Related Workmentioning

confidence: 99%

Power optimization in heterogenous datapaths

Barrio

Memik

Molina

et al. 2011

2011 Design, Automation &Amp; Test in Europe

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“…Hence, PABCOM considers the interrelation between the behavioural synthesis tasks (scheduling and binding) and the clock and operations throughput selection. In this paper, the term throughput is used in the same context than in [9], i.e. to refer to the number of control steps (csteps) that an operation requires to be executed.…”

Section: Pabcommentioning

confidence: 99%

“…PABCOM is a power-aware behavioural compiler based on the novel scheduling and datapath synthesis algorithms presented in [10] and [9] respectively. Hence, PABCOM considers the interrelation between the behavioural synthesis tasks (scheduling and binding) and the clock and operations throughput selection.…”

Section: Pabcommentioning

confidence: 99%

Design of a low power MPEG-1 motion vector reconstructor

Ochoa-Montiel

Al-Hashimi

Kollig³

2009

Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes

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This paper describes the design of a low power MPEG-1 motion vector reconstructor using behavioural synthesis methodology. Various techniques, such as appropriate voltage scaling after clock and operations throughput selection, and reduction of multiplexer-based interconnection complexity are used to reduce power consumption. The design has been implemented based on a library components previously synthesised using Synplify ASIC w design has been performed through timing simulation with ModelSim, whereas power analysis is based on the reports obtained with PrimePower from Synopsys. The proposed design dissipates 42% less power than a power unaware design operated at the maximum supply voltage of the library components, i.e. 1.32V.

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