Impact of Loop Tiling on the Controller Logic of Acceleration Engines

Dutta, Hritam; Zhai, Jiali Teddy; Hannig, Frank; Teich, Jürgen

doi:10.1109/asap.2009.21

Cited by 4 publications

(2 citation statements)

References 16 publications

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“…Such controllers are in charge of orchestrating data transfer and computations for processor arrays, and they are based on the use of counters, decoders, address generators, and glue logic for interfacing the processor array to other components integrated in systemon-a-chip (SoC) environments. However, the data I/O is only proposed to be done either by functional simulation, by direct memory access (DMA), or by software running on a host processor [12]. Moreover, PARO cases of study include MatMul, FIR filter, discrete cosine transform and images filters.…”

Section: Input Specification In a Piecewise Regular Algorithm Formmentioning

confidence: 99%

Processor arrays generation for matrix algorithms used in embedded platforms

Perez-Andrade

Torres-Huitzil

Cumplido

et al. 2013

2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig)

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Matrix algorithms are an important part of many digital signal processing applications as they are core kernels that usually need to be applied many times. Hardware assisted implementations using FPGAs provide a good compromise between performance, cost and power consumption. This paper presents a high level synthesis approach to generate embedded processor arrays for matrix algorithms based on the polytope model. The proposed approach provides a solution for efficient data memory accesses and data transferring for feeding the processor array, as well as it provides support for solving a set of problem size depending on FPGA available resources. The proposed approach has been validated by generating processor arrays for two case studies targeted for a Spartan-6 device. Results show that the implemented array outperforms hardware and software implementations targeted to embedded platforms as well.

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Section: Input Specification In a Piecewise Regular Algorithm Formmentioning

confidence: 99%

Processor arrays generation for matrix algorithms used in embedded platforms

Perez-Andrade

Torres-Huitzil

Cumplido

et al. 2013

2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig)

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“…Dutta et al in [10] provide a methodology for automatic generation of control engines in charge of orchestrating data transfer and computations for processor arrays generated by the PARO framework [2]. They describe a scheme for the memory controller synthesis based on the use of counters, decoders, address generators, and glue logic for interfacing the processor array to other components integrated in a system-on-a-chip (SoC) environment.…”

Section: Related Workmentioning

confidence: 99%

On an external memory scheme for processor arrays

Perez-Andrade

Torres-Huitzil

Cumplido

et al. 2013

IEICE Electron. Express

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Abstract:The problem of generating memory interfaces between loop-based accelerators and external memory is gaining the attention from the high-level synthesis research community. This paper presents an external memory system for inserting/extracting data to/from a loop-based accelerator derived by a high-level synthesis approach. The memory system is composed by four architectural cases which could occur during hardware synthesis. The memory system is based on a global asynchronous local synchronous approach and the use of dualport memory banks. FPGA-based implementation results show that the proposed memory system is technologically achievable and provides a high-bandwidth without introducing communication overhead.

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