Impact of line-edge roughness on resistance and capacitance of scaled interconnects

Stucchi, M.; Bamal, Mandeep; Maex, Karen

doi:10.1016/j.mee.2007.05.038

Cited by 39 publications

(13 citation statements)

References 4 publications

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“…According to ITRS [4], LER and LWR of sub-10 nm nanostructures are requested to be lower than 0.6 and 0.8 nm, respectively, because higher values could be highly detrimental for the performance of the resulting microelectronics devices [94][95][96][97]. Figure 11(c) reports the LER and LWR literature values of sub-10 nm PDMS parallel cylindrical nanostructures, in self-assembled PS-b-PDMS thin films treated by different annealing methods.…”

Section: Discussionmentioning

confidence: 99%

Technological strategies for self-assembly of PS-b-PDMS in cylindrical sub-10 nm nanostructures for lithographic applications

Giammaria

Laus

Perego³

2018

Advances in Physics: X

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The continuous demand for small portable electronics is pushing the semiconductor industry to develop novel lithographic methods to fabricate the elementary structures for microelectronics devices with dimensions below 10 nm. Topdown strategies include multiple patterning photolithography, extreme ultraviolet lithography (EUVL), electron beam lithography (EBL), and nanoimprint lithography. Bottom-up approaches mainly rely on block copolymers (BCPs) self-assembly (SA). SA of BCPs is extremely appealing due to its excellent compatibility with conventional photolithographic processes, high-resolution patterns, and low process costs. Among the various BCPs, the polystyrene-b-polydimethylsiloxane (PS-b-PDMS) represents the most investigated material for the fabrication of sub-10 nm structures. However, PS-b-PDMS cannot be easily processed by conventional thermal treatments due to its slow SA kinetic coupled with a relatively low thermal stability. This review focuses on the available annealing methods to promote the SA PS-b-PDMS in parallel-oriented cylindrical sub-10 nm structures. Moreover, literature data regarding the annealing time, defects density, line edge roughness (LER) and line width roughness (LWR) are discussed with reference to the stringent requirements of semiconductor technology.

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Section: Discussionmentioning

confidence: 99%

Technological strategies for self-assembly of PS-b-PDMS in cylindrical sub-10 nm nanostructures for lithographic applications

Giammaria

Laus

Perego³

2018

Advances in Physics: X

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“…The increasing shrinking and miniaturization of device sizes is leading to a non-negligible impact of line-edge roughness (LER) on mm-wave and nanoscale on-chip interconnects [1]. LER is introduced by several sources in the manufacturing process, including photolitographic mask uncertainties and chemical properties of resist [2].…”

Section: Introductionmentioning

confidence: 99%

An Effective Modeling Framework for the Analysis of Interconnects Subject to Line-Edge Roughness

Manfredi

Ginste

Zutter

2015

IEEE Microw. Wireless Compon. Lett.

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Abstract-This letter proposes a complete and efficient simulation framework to assess the effects of line-edge roughness appearing in on-chip lines. The modeling approach consists of three steps. First, a stochastic macromodel is created for the per-unit-length RLGC parameters of the line. Secondly, random conductor edge profiles are generated using randomized splines. These are combined with the stochastic macromodel to readily provide place-dependent RLGC parameters. Finally, the resulting nonuniform transmission line is analyzed by means of a fast and accurate perturbation technique. To validate the proposed approach, a statistical analysis of the response of a coupled inverted embedded microstrip line is carried out for different roughness parameters.

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“…Furthermore, LER values for patterning at 32 or 22 nm nodes is yet to reach the goals set by the ITRS for immersion double patterning or EUV. Given that LER can have a significant effect on device performance, [26] it still remains important to develop polymers and processes that minimize LER and also to gain further understanding of the processes involved.…”

Section: Introductionmentioning

confidence: 99%

Sensitive polysulfone based chain scissioning resists for 193nm lithography

et al. 2011

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Chain scissioning resists do not require addition of photoacid generators to function. Previously reported chain scissioning polysulfone resists were able to achieve enhanced sensitivity by incorporation of absorbing repeat units, but these groups also inhibited the depolymerization reaction, which could further enhance sensitivity. Here we report the development of sensitive polysulfone chain scissioning resists for 193 nm that are able to undergo depolymerization. The effect of depolymerization of LER is also discussed. These polymers underwent CD shrinkage upon overdose, which may be useful for double patterning processes.

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Impact of line-edge roughness on resistance and capacitance of scaled interconnects

Cited by 39 publications

References 4 publications

Technological strategies for self-assembly of PS-b-PDMS in cylindrical sub-10 nm nanostructures for lithographic applications

Technological strategies for self-assembly of PS-b-PDMS in cylindrical sub-10 nm nanostructures for lithographic applications

An Effective Modeling Framework for the Analysis of Interconnects Subject to Line-Edge Roughness

Sensitive polysulfone based chain scissioning resists for 193nm lithography

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