Impact of Layout, Interconnects and Variability on CMOS Technology Roadmap

Bœuf, F.; Sellier, Manuel; Farcy, A.; Skotnicki, T.

doi:10.1109/vlsit.2007.4339712

Cited by 9 publications

(3 citation statements)

References 2 publications

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“…It is widely recognized that random dopant fluctuations in scaled planar bulk devices will be a major roadblock for the integration of these devices in high density 6T SRAM cells [1,2]. The possibility of leaving the channels undoped and their excellent immunity against Short Channel Effects (SCE) favors the use of FinFETs [3].…”

Section: Introductionmentioning

confidence: 99%

Low-voltage 6T FinFET SRAM cell with high SNM using HfSiON/TiN gate stack, fin widths down to 10nm and 30nm gate length

Collaert

Arnim

Rooyackers

et al. 2008

2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial

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Section: Introductionmentioning

confidence: 99%

Low-voltage 6T FinFET SRAM cell with high SNM using HfSiON/TiN gate stack, fin widths down to 10nm and 30nm gate length

Collaert

Arnim

Rooyackers

et al. 2008

2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial

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“…The same improvement is also seen in the patterning of all critical levels of the 45 nm node 0.24 mm 2 SRAM cell. 9) Figure 13 shows also an example of the active level printed with and without R-EBPC with a 55 nm target CD and 130 nm pitch. In general, the application of R-EBPC improves the process window, allows a local control such as contact pads and decreases the line end loss.…”

Section: Application To Real Circuitsmentioning

confidence: 99%

New Electron Beam Proximity Effects Correction Approach for 45 and 32 nm Nodes

Manakli

Docherty

Pain

et al. 2006

jjap

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After the successful results obtained these last years, electron beam direct write (EBDW) lithography use for integrated circuit manufacturing has now been demonstrated. However, throughput and resolution capabilities need to be improved to push its interest for fast cycle production and advanced research and development applications. In this way, the process development needs good patterns dimensional accuracy, i.e., a better control of the proximity effects caused by back scattering electrons and others phenomenon. It exists several methods to provide a correction for these effects and the most commonly used is based on dose modulation. However it has been observed that this correction is not perfect and can significantly fail to accurately correct the smallest and most dense structures encountered in sub 65 nm design features. To continue reducing feature sizes a method to provide a complementary correction to the dose modulation solution is proposed. Based upon detailed characterization of the observed effects a rules correction scheme has been developed not dissimilar to the rule based corrections used in optical proximity correction (OPC). This rule based electron beam proximity correction, or R-EBPC, provides good results down to 40 nm, with improvements in critical dimension (CD) linearity, the isolated dense bias, line end shortening and the energy latitude. All of which leads to an improvement in the overall accuracy of the design, and furthermore an improvement in the process window.

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“…However, such an approach is not applicable to analog and mixed-signal circuits. MASTAR [6] is another platform used extensively for benchmarking devices at the end of CMOS roadmap [7]. MASTAR was used to evaluate the performance of digital and analog circuits at sub-0.5 11m regime by the use of Voltage-Doping Transformation (VDT) to model the threshold voltage [8].…”

Section: Introductionmentioning

confidence: 99%

Auto-BET-AMS: An automated device and circuit optimization platform to benchmark emerging technologies for performance and variability using an analog and mixed-signal design framework

Sachid

Thakker

Sathe

et al. 2010

2010 11th International Symposium on Quality Electronic Design (ISQED)

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In this paper, we present Auto-BET-AMS, an automated device, circuit and system-level simulation platform suitable for benchmarking emerging technologies at the end of the CMOS roadmap. This platform is suitable for technologists and circuit designers alike. One of the features of Auto-BET-AMS is that no advanced knowledge of device and circuit design is needed to perform a fair evaluation of emerging technologies. To enable this, the platform comes with a versatile multi-variable optimizer that can be used to quickly optimize devices and circuits for a set of specifications. Using Auto-BET-AMS it is possible to accurately design digital and analog circuits and assess them in conventional and emerging technologies. The platform can handle definitions of chargebased devices in either the compact model form or a look-up table form. The latter is needed for devices which do not have mature compact models developed for them. Several representative digital and analog circuits like buffer chain, SRAM cell, two-stage Miller Op-Amp, three-stage lowvoltage Op-Amp, temperature compensated current reference and Miller OTA are optimized by considering PVT variations using Auto-BET-AMS. Additionally, the impact of parametric variations on these circuits is studied. IntroductionAt the end of the CMOS roadmap, a large number of interesting device concepts like UTB-SOI MOSFET [1], Schottky-Barrier MOSFET [2], Tunnel FET [3], FinFET [4] etc, have emerged as possible alternatives for the mainstream bulk MOSFET technology. Among these devices, UTB-SOI MOSFET and FinFET devices are promising. A fair comparison between various technologies at the device, circuit and system-level is essential in order to assess the true potential of these technologies. For this, not only parasitics at the device level but also the impact of interconnects and parametric variability should be included. Technology development is a highly iterative process which involves tweaking a combination of the device characteristics, circuits and architecture design. With multiple competing technology choices at the lower technology nodes, it is essential to have a fast, accurate and efficient platform to benchmark emerging technologies.Technology CAD (TCAD) is used extensively for device optimization. Essentially a TCAD tool predicts the performance of devices by solving the Poisson and continuity equations using a set of boundary conditions. TCAD is also capable of predicting the behavior and performance of circuits. Circuit simulations using TCAD are time consuming as it has to solve simultaneous device equations for all the devices in the circuit. On the other hand, circuit simulation using compact models is time-efficient and has been used extensively for circuit design and optimization. In dedicated

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Impact of Layout, Interconnects and Variability on CMOS Technology Roadmap

Cited by 9 publications

References 2 publications

Low-voltage 6T FinFET SRAM cell with high SNM using HfSiON/TiN gate stack, fin widths down to 10nm and 30nm gate length

Low-voltage 6T FinFET SRAM cell with high SNM using HfSiON/TiN gate stack, fin widths down to 10nm and 30nm gate length

New Electron Beam Proximity Effects Correction Approach for 45 and 32 nm Nodes

Auto-BET-AMS: An automated device and circuit optimization platform to benchmark emerging technologies for performance and variability using an analog and mixed-signal design framework

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