Impact of Interface Traps on Negative Capacitance Transistor: Device and Circuit Reliability

Abstract

In this work, we investigate the impact of Si-SiO2 interface traps on the performance of negative capacitance transistor, which is a promising emerging technology that aims at achieving a steep sub-threshold slope. Interface traps induced degradation is well known to be one of the major concerns when it comes to reliability. We focus on investigating the impact of different interface trap concentrations on the figures of merit of both the devices and circuits. Our investigation is performed using TCAD models, which are well calibrated against 14 nm production quality FinFETs. This allows accurate analysis and modeling of the impact of NC on the electric field across the SiO2 layer. Then, the industry compact model of FinFET (BSIM-CMG) is fully calibrated to reproduce TCAD data. In addition, a physics-based NC model is integrated and solved self-consistently within the BSIM-CMG model in which TCAD data of NC-pFinFETs and NC-nFinFETs are also well matched. This allows studying how interface traps induced degradation can impact circuits. Our results demonstrate that the amplified electric field across the SiO2 layer within NC-pFinFET due to NC effect leads to a higher interface trap concentration. This, in turn, results in a larger degradation in the NC-pFinFET compared to its pFinFET counterpart -when both of these devices are operated at the same nominal supply voltage of the 14 nm node. However, at the same interface trap concentration, the NC-pFinFET always exhibits less degradation than the baseline pFinFET due to the former's better electrostatic integrity on account of voltage amplification effect. With respect to circuits, we study both Ring Oscillator (RO) and 6-T SRAM cell circuits. We show how the frequency of RO in the case of NC-FinFET is always less impacted by interface trap induced degradations compared to its counterpart FinFET-based RO. For 6-T SRAM cell, we demonstrate how the key reliability metrics such as hold noise margin, read noise margin, and write noise margin are also less impacted by the induced degradations in NC-FinFET SRAMs compared to the baseline FinFET SRAMs. This is because of the much better electrostatic integrity that NC provides.

Reliability physics of ferroelectric/negative capacitance transistors for memory/logic applications: An integrative perspective

“…1) Bias Temperature Instability (BTI), i.e., V th shift due to charge trapping, plays a role in FeFETs [30], [57] as well as NCFETs [46], [48]. V th -shifts due to BTI can either cause fast, recoverable issues [30], [57] (i.e., causing instability) or permanent damage (related to trap generation) limiting reliability [28], [35], [40], [46].…”

“…As pointed out in [48], due to the internal voltage amplification NCFETs would be more prone to interface trap generation than the corresponding MOSFETs (i.e., at the same node without the ferroelectric layer) if operated at the same supply voltage. On the other hand, at a given interface trap concentration (or equivalently, stress time) NCFETs have lower ΔV th than MOSFETs 6 [48], as also explained previously. Hence, in practice NCFETs should be operated at lower supply voltage than their MOSFETs counterparts to slow down aging.…”

Impact of NCFET on Neural Network Accelerators

“…(3) Interface Traps Effects: In [36], we studied the impact of interface traps on the device characteristics of NCFET compared to the baseline transistor using calibrated TCAD simulations. Our analysis showed that, at the same interface trap concentration, the NCFET always exhibits less degradation than the baseline transistor due to the better electrostatic integrity caused by the negative capacitance effect.…”

Analytical Current–Voltage Modeling and Analysis of the MFIS Gate-All-Around Transistor Featuring Negative-Capacitance

“…Recently, an NC GAA-FET having a metal-ferroelectric-insulator-semiconductor (MFIS) type has been investigated by introducing NC characteristics to a gate stack as a nextgeneration semiconductor in a GAA transistor [19,20]. In addition, it has been reported that interface traps at the Si-SiO 2 interface can result in the degradation of transistor performance (e.g., sub-threshold swing) [21], the process-variable ∆V th [22], and negative bias temperature instability (NBTI)-induced ∆V th [23]. This interface trap effect has been considered important from before in silicon GAA-FET without ferroelectric material, and compact modeling methodologies have been proposed [24].…”