Impact of interface traps on performance of Gate-on-Source/Channel SOI TFET

Mitra, Suman Kr.; Bhowmick, Brinda

doi:10.1016/j.microrel.2019.01.004

Cited by 18 publications

(6 citation statements)

References 35 publications

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“…This has attributed a higher FOM to the former. Similarly, for CG TFET 16 and GOSC (Gate on Source/Channel) TFET, 25 nearly all the parameters for the latter are superior to that of the former. Therefore, GOSC TFET has a higher FOM.…”

Section: |mentioning

confidence: 92%

Perspective—Performance Assessment of TFETs for Low Power Applications: Challenges and Prospects

Shukla¹,

Goswami²

2020

ECS J. Solid State Sci. Technol.

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Tunnel Field Effect Transistors (TFETs) are potential semiconductor devices which offer low off current, sub-60 mV dec −1 subthreshold swing and significantly alleviated short channel effects, as compared to downscaled MOSFETs. However, the low on current in TFETs has been a major challenge which has propelled the direction of research towards proposals of novel geometries. The emergence of a number of geometries and their detailed optimizations creates a number of challenges for selecting the best one among them. This work presents the different challenges and offers an effective solution through the discussion involving a figure of merit.

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Section: |mentioning

confidence: 92%

Perspective—Performance Assessment of TFETs for Low Power Applications: Challenges and Prospects

Shukla¹,

Goswami²

2020

ECS J. Solid State Sci. Technol.

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“…This variation mainly happens owing to the fluctuations in the flat-band voltage (V FB ) exhibiting high sensitivity regarding to polarity and density variation in ITCs. The dependency of V FB on density of ITCs (N f ) can be mathematically expressed as [6]:…”

Section: Influence Of Itcs On DC Performancementioning

confidence: 99%

“…Some researchers have experimented on various techniques to improve the ON-state current and downscaling ambipolarity. These approaches often involve optimizing the device structure, including different materials to form hetero junction at S/C interface [4], graded-channel [5], gate-on-source for better controllability [6], Gaussian profile doping towards drain side [7], source and pocket engineering to optimize the depletion width [8], gate voltage modulation with negative capacitance [9] In particular, gate-all-around (GAA) structures for TFET have been widely studied owing to improvements in gate controllability over the channel. The tunneling width of a double gate and GAA-TFET is represented as equations (1) and (2), respectively [10].…”

Section: Introductionmentioning

confidence: 99%

Interfacial charge and temperature analysis of gate-all-around line tunneling TFET for improved device reliability

Karthik,

Pandey

2024

Phys. Scr.

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In this article, the impact of interface-trap charges (ITCs) on the DC and analog/RF parameters of gate-all-around vertical TFET (GAA-VTFET) are considered to evaluate the reliability of the device. ITCs are included at oxide/semiconductor interface of GAA-VTFET where the probability of occurrence of traps are high owing to faults in the manufacturing process. A detailed investigation is carried out by tuning the temperature, polarities and density of ITCs. It is clearly observed from TCAD based simulation results that the presence of traps alters the flat-band voltage, thereby affecting the overall performance of the device. Transfer characteristics of the device depicts that impact of traps shows more variation in the OFF-state current than the ON-current. However, presence of donor traps improves the analog/RF parameter, such as parasitic capacitances (Cgg), Transconductance (gm), cut-off frequency (fT), output resistance (Rout) etc. Furthermore, the simulation results proclaim that GAA-VTFET shows more resilient to acceptor traps than the positive traps. Moreover, by examining the influence of ambient temperature on device performance, it is revealed that the drain current in the subthreshold region (at low gate bias) is more susceptible to the degradation than the super-threshold region at elevated temperature. This is mainly due to the superiority of the trap-assisted tunneling (TAT) and Shockley-Read-Hall (SRH) recombination mechanisms over the band-to-band tunneling (BTBT). When the raise in ambient temperature is tuned between minimum of 200 K to maximum of 400 K, it is observed that OFF-current increases by ∼7 times. Lastly, voltage-transfer characteristics (VTC) analysis of the resistive-load inverter clearly demonstrates that the influence of traps on the noise margin is within acceptable limits.

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“…In our simulation we considered acceptor type traps for the various analyses. This is because donor type traps have been found to have an insignificant effect on device characteristics whereas acceptor type traps have a greater effect on the current of a device, which also directly influences the transconductance [29,31,36,37]. With regard to the capture cross section, the traps are considered to be at the oxidesemiconductor interface of our proposed structure because degradation due to traps is mainly caused by interface traps located around the tunneling area, leading to a lowering of the tunneling field and transconductance, and thereby the drain current [36].…”

Section: Impact Of Itc Under the Influence Of Temperature On Transfer...mentioning

confidence: 99%

Interface trap-induced radiofrequency and low-frequency noise analysis under temperature variation of a heterostacked source L-gate tunnel field effect transistor

Das,

Chakraborty,

Borah

2024

Semicond. Sci. Technol.

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This brief exclusively demonstrates a comprehensive analysis of the adverse impact of interface trap charge (ITC) under the influence of temperature variation on a hetero-stacked (HS) source L-gate tunnel field effect transistor (TFET) having SiGe pocket. An investigation of both static and RF characteristics has been carried out. It appears that ITCs situated at the Silicon (Si)/oxide interface fluctuates the flat-band voltage to alter the various analog/RF parameter characteristics. Uniform ITCs are seen to be less susceptible to degradation in device characteristics. The low frequency noise (LFN) analysis has also been investigated considering the impact of different trap distribution (Uniform and Gaussian) and densities which are compared thereafter. Besides, the temperature dependent LFN has been studied under influence of different distributed ITCs which is rarely explored yet. Moreover, a comparative analysis has been done on the device behaviour and LFN characteristics of HS L-gate TFET structures with and without SiGe pocket. The structure with SiGe pocket is found to be insusceptible to noise effects.

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Impact of interface traps on performance of Gate-on-Source/Channel SOI TFET

Cited by 18 publications

References 35 publications

Perspective—Performance Assessment of TFETs for Low Power Applications: Challenges and Prospects

Perspective—Performance Assessment of TFETs for Low Power Applications: Challenges and Prospects

Interfacial charge and temperature analysis of gate-all-around line tunneling TFET for improved device reliability

Interface trap-induced radiofrequency and low-frequency noise analysis under temperature variation of a heterostacked source L-gate tunnel field effect transistor

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