Impact of hump effect on MOSFET mismatch in the sub-threshold area for low power analog applications

Active “multi-fingers”: Test structure to improve MOSFET matching in sub-threshold area

“…Therefore, as plotted in Fig. 8(b), gate voltage matching is well improved thanks to this much bigger total equivalent area as expected by (5). Analog applications are often biased under threshold for low power concerns and matching performances.…”

“…7 (m is the number of identical transistor placed in parallel). As a consequence, the total area of parasitic devices is increased by a factor m and the worst value for the gate voltage matching is so given by (5): AVT <Jell VG)= (5) .Jm. 2WHUMP• L Therefore, more the number m of transistors placed in parallel is important, the better will be the gate voltage matching in sub-threshold region (decreased of factor -vrn)…”

“…1. This hump effect can strongly degrades matching performances in sub-threshold area [5]. In this context, an active "multi-fingers" test structure is proposed to improve gate voltage matching.…”

Benchmarking and optimization of trench-based multi-gate transistors in a 40 nm non-volatile memory technology

“…Therefore, all these contributions activate the parasitic transistor at the active/trench corner with a reduced threshold voltage. This effect has an impact on the subthreshold region and can explain the IOFF leakage current increase for the TGT architectures [12].…”

Multi-Level Control of Resistive RAM (RRAM) Using a Write Termination to Achieve 4 Bits/Cell in High Resistance State

“…In this analysis, only actual possible variations are reported, since cell variability is generated based on a targeted OxRAM technology. Moreover, the variability (including transistor mismatch [28,29]) targets the CMOS subsystem and especially the memory cell access transistor as its impact on the memory cell electrical characteristics is dominant [30]. Process variation parameters used for CMOS transistors are provided by ST-Microelectronics (Crolles, France).…”