Impact of Hot Carriers on nMOSFET Variability in 45- and 65-nm CMOS Technologies

Design of CMOS logic gates with enhanced robustness against aging degradation

“…This process results in a shift in the threshold voltage, transconductance degradation, and decreasing of the transistor drain current drive capability. Due to the fact that the mobility of the electrons is higher than the holes, NMOS transistors are more degraded than PMOS ones [12]. For a specific technology node and for a given set of environmental conditions, the DV th_HCE can be expressed by the following equation, as a function of the transistor switching HCE degradation probability (TSwP) [12]:…”

From Atoms to Circuits: Theoretical and Empirical Modeling of Hot Carrier Degradation

“…HCD induced [34] stress is shown (Fig. 4) to cause higher sub-threshold slope variability (an order of magnitude) compared with Vt-variability [33]. In that work, at the failure criterion of 4V t D 50 mV, the increase in 4V t spread was found to be 15 % relative to a 4S (change in sub-threshold slope) spread of 150 %.…”

“…There are several such studies in the literature. In these studies, HCD induced variability has been found to be stress voltage independent [33,34]: the overall level of shift is sufficient to capture the variability. Magnone showed the HCD variability data collected in 45 and 65 nm hardware to follow a Gaussian distribution.…”

Interpretation of MOS transistor mismatch signature through statistical device simulations

“…it happens in case of fresh devices. This phenomenon is due to an increase of the subthreshold slope variations in the stressed devices compared to fresh ones, the threshold voltage mismatch remains in fact basically unaltered [82]. It must be noted that the shape of the autocorrelation plot after stress is remarkably similar to the simulation with RIF first version (see figure 3.7).…”

“…The device were stressed for 100 s applying 2.4 V on the drain and 1.2 V on the gate. This stress resulted in a typical average V T shift of approximately 40 mV, which was sufficient to generate enough traps to affect the mismatch signatures [82].…”