Design of CMOS logic gates with enhanced robustness against aging degradation

BTI and HCI first-order aging estimation for early use in standard cell technology mapping

“…Long term models explore the stress condition probabilities to compute the V th degradation [12]. For specific technology node and a given set of environmental conditions, the DV th _ BTI can be expressed by the following equation, as a function of the transistor stress probability (TSP) [10]:…”

“…The severity of HCI is related exponentially to the transistor drain-to-source voltage (V ds ) [4]. For a specific technology node and for a given set of environmental conditions, DV th_HCI can be expressed by the following equation, as a function of the transistor switching HCI degradation probability (TSwP) [10]:…”

“…TSwP is the probability of the transistor to suffers HCI degradation. TSwP depends on the transistor switching probability and on the position of the transistor in the network arrangement, as discussed in [10].…”

“…At gate level, there are techniques that add a time slack margin to compensate the degradation by upsizing the transistors width [8], whereas other methods focus on the intrinsic robustness of transistor network arrangement [9]. The choice of CMOS gates designed in single and multiple stages is also investigated in [10].…”

“…One candidate for such design cost is the average gate delay degradation due to aging effects. Such degradation is strongly influenced by the transistor arrangements and by the number of stages in logic gates, as discussed in [10]. However, the method presented in [10] to obtain this information for each logic gate is quite expensive as a large number of SPICE simulations is required.…”