Impact of HK / MG stacks and future device scaling on RTN

Abstract

This work demonstrates the close relationship between device scaling and the threshold voltage variation (ΔV th ) of random telegraph noise (RTN) in high-κ and metal gate (HK / MG) stacks. Statistical analysis clarifies that high temperature forming gas annealing can suppress the RTN ΔV th . And properly annealed HK FETs have smaller RTN ΔV th than SiON FETs, due mostly to fewer traps and partly to thinner inversion thickness in HK / MG stacks. Consequently, the influence of RTN on HK / MG gate stacks is less than that of random dopant fluctuation in the 22 nm generation. However, RTN may pose a difficult challenge for the 15 nm generation. In addition to the scaling dependence, we also find that characterizing hysteretic RTN behaviors due to RTN dependence on bias is essential to determine whether the observed RTN has an impact on SRAM operation or not.

A Dual-Point Technique for the Entire ID–VG Characterization Into Subthreshold Region Under Random Telegraph Noise Condition

“…Towards the vertical and horizontal directions, ΔID represents the current variation in VGH and VGL respectively, ΔID(VGH) and ΔID(VGL). Recent results [20] confirm that ΔID in linear region is much larger than in subthreshold region. Therefore, the large gap in vertical direction created by ΔID(VGH) makes the two clusters distinguishable even there is tiny gap in the horizontal direction.…”

“…andom Telegraph Noise (RTN) has become one standard test for future ultra-scaled transistors [1][2][3]. However, the standard RTN procedure [4] only captures the current under constant gate voltage, VG_RTN, which contains limited information.…”

Set level at speed HTOL test for reliability qualification of high speed mobile applications

“…Reduced time of development (time to market) while ensuring quality and robustness against field failure initiates a savvy way of performing mobile product qualification study extended to the set level stress presented here. Still, further study is being conducted to identify the exact physical mechanism associated with such application dependent failure that might be associated with circuit racing conditions or perhaps RTN in scaled technologies [5,6]. Either of these can also be handled with design-in for quality and some guard-band.…”

The improvement of the 2nd dummy poly gate removal with the optimized WAC condition

“…The gate-last approach has been widely adopted since it can better control the transistor threshold voltage (Vt) and yield better electrical performance. [1][2] However, this approach requires more complex process engineering than gate-first approach. It has challenged every process of metal gate loop, especially in the removal of the second dummy gate.…”