Impact of Geometry, Doping, Temperature, and Boundary Conductivity on Thermal Characteristics of 14-nm Bulk and SOI FinFETs

Sun, Jun-Ya; Li, Xiaojin; Sun, Yabin; Shi, Yanling

doi:10.1109/tdmr.2020.2964734

Cited by 30 publications

(6 citation statements)

References 19 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The values of SS and DIBL are, respectively, 61 mV/dec and 43.32 mV/V for the 14-nm n-FinFET. These parameters are approximately maintained the same as the ones reported in papers [1][2][3][4].…”

Section: Device Validationmentioning

confidence: 70%

“…Figure 1 shows the 3D schematic diagram of the FinFET device with a physical gate length (L g ) of 20 nm. The geometrical parameters and material properties are specified in previously published papers [1][2][3]. HfO 2 is used as a gate dielectric material.…”

Section: Device Structurementioning

confidence: 99%

“…The device characteristics of the investigated model are compared to the experimental outputs [1] and presented in Table 2. To further validate the developed model, the simulation results were compared also to Sun's work [2]. Figure 3 presents the output I-V characteristics of the investigated model at different gate-source voltages.…”

Section: Device Validationmentioning

confidence: 99%

“…Furthermore, the hafnium oxide was used as a gate dielectric material. There are full-node processes for FinFET technologies, such as 16, 14, 10, 7, 5, and 3 nm in R&D [1,2]. Thus, is very important to investigate the effect of the gate length on calibrated FinFET device performance.…”

Section: Impact Of the Gate Length On Device Performancementioning

confidence: 99%

“…The structure of the fin field-effect transistor (FinFET) has completely emerged as a promising design solution for CMOS logic and memory circuit design because of its good immunity to short channel effects (SCEs) [1][2][3]. This technology enables the creation of high-performance ultra-scaled, high-density integration, and high-performance silicon (Si) chips [1][2][3][4]. In the silicon industry, device miniaturization is still considered a key feature to achieve better short-channel performance.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Effects of Varying the Fin Width, Fin Height, Gate Dielectric Material, and Gate Length on the DC and RF Performance of a 14-nm SOI FinFET Structure

et al. 2021

View full text Add to dashboard Cite

The FinFET architecture has attracted growing attention over the last two decades since its invention, owing to the good control of the gate electrode over the conductive channel leading to a high immunity from short-channel effects (SCEs). In order to contribute to the advancement of this rapidly expanding technology, a 3D 14-nm SOI n-FinFET is performed and calibrated to the experimental data from IBM by using Silvaco TCAD tools. The calibrated TCAD model is then investigated to analyze the impact of changing the fin width, fin height, gate dielectric material, and gate length on the DC and RF parameters. The achieved results allow gaining a better understanding and a deeper insight into the effects of varying the physical dimensions and materials on the device performance, thereby enabling the fabrication of a device tailored to the given constraints and requirements. After analyzing the optimal values from different changes, a new device configuration is proposed, which shows a good improvement in electrical characteristics.

show abstract

Section: Device Validationmentioning

confidence: 70%

Section: Device Structurementioning

confidence: 99%

Section: Device Validationmentioning

confidence: 99%

Section: Impact Of the Gate Length On Device Performancementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Effects of Varying the Fin Width, Fin Height, Gate Dielectric Material, and Gate Length on the DC and RF Performance of a 14-nm SOI FinFET Structure

et al. 2021

View full text Add to dashboard Cite

show abstract

Temperature‐Induced Changes in Multifin‐Schottky Barrier FinFETs: An Analog/RF Linearity Investigation

Shalini,

Kumar

2024

Advcd Theory and Sims

View full text Add to dashboard Cite

In this script, a Gallium Nitride (GaN)‐based FinFET structure is proposed with a multi‐channel device that is designed and simulated. Here, the 3D‐Sentaures TCAD simulator is used to investigate the analog/radio frequency performance and linearity of the MultiFin‐Schottky Barrier FinFET with different temperatures of 100–400 K. The proposed device underwent a temperature analysis, where critical parameters include drain current, ION/IOFF ratio, Transconductance (gm), higher‐order terms (gm2 and gm3), Gain Bandwidth Product (GBP), Cut‐off Frequency (fT), Transit Time (τ), Transconductance Generation Factor (TGF), Transconductance Frequency Product (TFP), Voltage Input Intercept Point (VIP2, VIP3), Input Intercept Point (IIP3), and Third Order Intermodulation Distortion (IMD3) is thoroughly examined. Thus, the proposed GaN‐based FinFET validates as a strong potential contender for GaN‐based analog/RF applications.

show abstract

Investigating the Impact of Self-Heating Effects on some Thermal and Electrical Characteristics of Dielectric Pocket Gate-all-around (DPGAA) MOSFETs

Purwar

Gupta

Tiwari

et al. 2021

Silicon

View full text Add to dashboard Cite

The dielectric pocket gate-all-around (DPGAA) MOSFET is being considered the best suited candidate for ULSI electronic chips because of excellent electrostatic control over the channel. However, the phenomena of self-heating and hot carrier injection (HCI) severely affect the performance of the device, and make the behaviour of the DPGAA FET very unpredictable. In the present article, a comprehensive investigation under the in uence of self-heating effects has been done for the variation in the lattice and carrier temperature against spacer length, ambient temperature, device length, and thermal contact resistance including ON and Off currents with gate bias voltage (V GS ). In order to analyse the SHEs, the hydrodynamic (HD) and thermodynamic (TD) transport models have been used for three-dimensional (3D) electrothermal (ET) simulation. The Lucky (hot carrier injection) model has been used to study the HCI degradation in DPGAA MOSFET using Sentaurus 3D TCAD simulator.

show abstract

Impact of Geometry, Doping, Temperature, and Boundary Conductivity on Thermal Characteristics of 14-nm Bulk and SOI FinFETs

Cited by 30 publications

References 19 publications

Effects of Varying the Fin Width, Fin Height, Gate Dielectric Material, and Gate Length on the DC and RF Performance of a 14-nm SOI FinFET Structure

Effects of Varying the Fin Width, Fin Height, Gate Dielectric Material, and Gate Length on the DC and RF Performance of a 14-nm SOI FinFET Structure

Temperature‐Induced Changes in Multifin‐Schottky Barrier FinFETs: An Analog/RF Linearity Investigation

Investigating the Impact of Self-Heating Effects on some Thermal and Electrical Characteristics of Dielectric Pocket Gate-all-around (DPGAA) MOSFETs

Contact Info

Product

Resources

About