Impact of free-surface passivation on silicon on insulator buried interface properties by pseudotransistor characterization

Hamaide, G.; Allibert, F.; Hovel, H. J.; Cristoloveanu, S.

doi:10.1063/1.2745398

Cited by 69 publications

(42 citation statements)

References 11 publications

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“…41 The applications of certain surface passivation techniques, such as hydrogen-termination 42 , can greatly reduce the density of these defects and increase the FET response of a Si nanowire channel. 43 An advantage of the MLD process developed in this study is that there is no damage to the nanowires, which might otherwise be caused by techniques such as ion implantation. Charge depletion caused by the presence of surface states can potentially limit the effective channel diameter of a nanowire.…”

Section: Carrier Profilingmentioning

confidence: 99%

Organo-arsenic Molecular Layers on Silicon for High-Density Doping

O’Connell

Verni

Gangnaik

et al. 2015

ACS Appl. Mater. Interfaces

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This article describes for the first time the controlled monolayer doping (MLD) of bulk and nanostructured crystalline silicon with As at concentrations approaching 2 × 10 20 atoms cm −3 . Characterization of doped structures after the MLD process confirmed that they remained defect-and damage-free, with no indication of increased roughness or a change in morphology. Electrical characterization of the doped substrates and nanowire test structures allowed determination of resistivity, sheet resistance, and active doping levels. Extremely high As-doped Si substrates and nanowire devices could be obtained and controlled using specific capping and annealing steps. Significantly, the As-doped nanowires exhibited resistances several orders of magnitude lower than the predoped materials.

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Section: Carrier Profilingmentioning

confidence: 99%

Organo-arsenic Molecular Layers on Silicon for High-Density Doping

O’Connell

Verni

Gangnaik

et al. 2015

ACS Appl. Mater. Interfaces

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“…In the case of SGOI with Ge% = 90%, a decrease in mobility was observed, although a high mobility value of around 400 cm 2 / V s was expected. This may be attributed to the influence of a top surface without passivation because the SiGe layer is less than 20 nm thick [5,12].…”

Section: The Effect Of Al 2 O 3 -Pda On the Electrical Properties Of mentioning

confidence: 95%

Effective passivation of defects in Ge-rich SiGe-on-insulator substrates by Al2O3 deposition and subsequent post-annealing

Yang

Iyota

Ikeura

et al. 2011

Solid-State Electronics

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a b s t r a c tA method of Al 2 O 3 deposition and subsequent post-deposition annealing (Al 2 O 3 -PDA) was proposed to passivate electrically active defects in Ge-rich SiGe-on-insulator (SGOI) substrates, which were fabricated using Ge condensation by dry oxidation. The effect of Al 2 O 3 -PDA on defect passivation was clarified by surface analysis and electrical evaluation. It was found that Al 2 O 3 -PDA could not only suppress the surface reaction during Al-PDA in our previous work [Yang H, Wang D, Nakashima H, Hirayama K, Kojima S, Ikeura S. Defect control by Al-deposition and the subsequent post-annealing for SiGe-on-insulator substrates with different Ge fractions. Thin Solid Films 2010; 518: 2342-5.], but could also effectively passivate p-type defects generated during Ge condensation. The concentration in the range of 10 16 -10 18 cm À3 for defect-induced acceptors and holes in Ge-rich SGOI drastically decreased after Al 2 O 3 -PDA. As a result of defect passivation, the electrical characteristics of both back-gate p-channel and nchannel metal-oxide-semiconductor field-effect transistors fabricated on Ge-rich SGOI were greatly improved after Al 2 O 3 -PDA.

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“…The threshold voltage appears to increase significantly in thinner films (12) where the coupling between the buried channel and the surface defects is amplified. The numerous charges and defects, located at the free wafer surface and associated with the native oxide, affect the Ψ-MOSFET characteristics which are no longer representative of the good quality film-BOX interface.…”

Section: Recent Soi Materials and ψ-Mosfet Measurementsmentioning

confidence: 98%

(Invited) The Pseudo-MOSFET: Principles and Recent Trends

et al. 2013

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The pseudo-MOSFET (Ψ-MOSFET) is a fascinating transistor based on the upside-down MOS configuration of semiconductor-on-insulator (SOI) wafers. This technique has been conceived for quick characterization of as-grown SOI materials. MOSFET-like characteristics are measured and simple parameter extraction techniques deliver the material properties: carrier mobility and lifetime, threshold and flat-band voltages, density of interface traps and oxide charges, doping level. After reviewing the methodology for reliable characterization, we focus on recent trends enabling the enrichment of the technique.

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Impact of free-surface passivation on silicon on insulator buried interface properties by pseudotransistor characterization

Cited by 69 publications

References 11 publications

Organo-arsenic Molecular Layers on Silicon for High-Density Doping

Organo-arsenic Molecular Layers on Silicon for High-Density Doping

Effective passivation of defects in Ge-rich SiGe-on-insulator substrates by Al2O3 deposition and subsequent post-annealing

(Invited) The Pseudo-MOSFET: Principles and Recent Trends

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