Impact of dual field plates on drain current degradation in InAlN/AlN/GaN HEMTs

Abstract

InAlN/AlN/GaN HEMTs with both source and gate dual field-plates (FPs) are proposed. To investigate the influence of dual FPs on the devices characteristics, two types of devices with gate FP and without FPs were fabricated and tested. The devices were subjected to different kinds of short-term direct current bias (DC-bias) stress conditions. The results show that after the off-state bias stress, the drain current reduction rate of the devices with dual FPs was 3.32%, which was less than that in both devices with a gate FP of 7.57% and devices without FPs of 14.63%. The current collapse of the HEMTs with dual FPs was relieved due to the increase of electric field uniformity between the gate and drain. The degradation of the output characteristics was more serious after the on-state bias stress. In addition, the effects of bias stress on the transfer characteristics of the devices were studied, and the trapping processes under different stress conditions in the devices were discussed.

Optimization AlGaN/GaN HEMT with Field Plate Structures

“…The source-drain voltage (Vds) varies from 0 V to 11 V, and the gate voltage (VG) varies from −4 V to 4 V. From the output curve, it can be seen that when VG = 4 V, the maximum saturation current (Ids) of no FP, G-FP, S-FP, and SG-FP are 476 mA/mm, 477.1 mA/mm, 487 mA/mm, and 494.7 mA/mm, respectively. The difference is small, which is related to the density of two-dimensional electron gas [ 16 ].…”

“…The transconductance (g m ) indicates the ability of the gate to regulate the channel current and also determines the switching speed of the device. The larger the transconductance, the faster the device switches [ 16 ]. In Figure 4 b, the transconductance is calculated by differentiating the results from the transfer characteristic curve, and the transconductance g m = 40.2 mS/mm, which is essentially the same.…”

Small-signal parameter extraction of asymmetric DCDMG AlGaN/GaN HEMT

“…Via-holes formation was performed using plasma dry etching to reduce source inductance. Field plate was formed to increase E-field uniformity and to reduce current collapse in device, as reported by Li et al (2016).…”