2022
DOI: 10.3390/mi13050702
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Optimization AlGaN/GaN HEMT with Field Plate Structures

Abstract: AlGaN/GaN HEMTs with several different designs of field plate structure are studied for device optimization purposes. To increase device breakdown voltage, optimal dimensions of field plates were first investigated using Silvaco TCAD software, and the electrical characteristics of the devices are analyzed. Several devices were designed and fabricated based on the simulation results. It has been confirmed that the gate-source composite field plate (SG-FP) has a higher breakdown voltage than other types of field… Show more

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Cited by 16 publications
(6 citation statements)
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References 18 publications
(20 reference statements)
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“…The reason is as follows: the introduction of the F-FP will cause slight changes in the gate-to-source capacitance and drain-to-gate capacitance of the device, and it only has a minor impact on the DC characteristics of the device. [32][33][34] Due to the positive bias of the F-FP (i.e., no channel depletion). 35,36 On the other hand the simulation is performed under ideal conditions.…”
Section: Simulation and Discussionmentioning
confidence: 99%
“…The reason is as follows: the introduction of the F-FP will cause slight changes in the gate-to-source capacitance and drain-to-gate capacitance of the device, and it only has a minor impact on the DC characteristics of the device. [32][33][34] Due to the positive bias of the F-FP (i.e., no channel depletion). 35,36 On the other hand the simulation is performed under ideal conditions.…”
Section: Simulation and Discussionmentioning
confidence: 99%
“…This contributes to the device’s longevity and stability. The common choices of the metal for the gate field plate are Ni/Au [ 41 ] or Ti/Au [ 42 ], both of which have excellent conductivity and adhesion.…”
Section: Devices’ Fabricationmentioning
confidence: 99%
“…A protective passivation layer of Si 3 N 4 is used to prevent surface state contamination and traps 25,26,27 . The parasitic capacitance under the gate terminal is lowered due to its reduced size and smaller field plate area 28–31 . The proposed device employing without field‐plate with gate recessed depths of 25, 30, and 35 nm and with field‐plate structure of 30 nm recessed gate depth are taken into consideration in this piece of research.…”
Section: Device Structure and Simulation Modelsmentioning
confidence: 99%