Impact of Cross-Sectional Shape on 10-nm Gate Length InGaAs FinFET Performance and Variability

Abstract

Three cross-sections (rectangular, bullet-like and triangular), resulting from fabrication process, of nanoscale In0.53Ga0.47As-on-insulator FinFETs with a gate length of 10.4 nm are modelled using in-house 3D finite-element densitygradient quantum-corrected drift-diffusion and Monte Carlo simulations. We investigate the impact of the shape on I-V characteristics and on the variability induced by Metal Grain Granularity (MGG), Line-Edge Roughness (LER) and Random Dopants (RDs) and compared to their combined effect. The more triangular the cross-section, the lower the off-current, the draininduced-barrier-lowering and the sub-threshold slope. The ION / IOF F ratio is 3 times higher for the triangular-shaped FinFET than for the rectangular-shape one. Independently of the crosssection, the MGG variations are the pre-eminent fluctuations affecting the FinFETs, with 4-to-2 times larger σVT than that from the LER and the RDs, respectively. However, the variability induced threshold voltage (VT) shift is minimal for the MGG (around 2.0 mV), but VT shift increases 4-fold and 15-fold for the LER and the RDs, respectively. The cross-section shape has a very small influence in VT and off-current of the MGG, LER and RD variabilities, both separated and in combination, with standard deviation differences of only 4% among the different device shapes. Finally, the statistical sum of the three sources of variability can predict simulated combined variability with only a minor overestimation.

Hybrid Silicon Nanowire Devices and Their Functional Diversity

“…[38,104,105] The extreme reduction in the semiconducting channel dimensions below 10 nm does not come at any cost. As it was also demonstrated by Seoane et al using nanoscale InGaAs, [110] the cross-sectional shape in FinFETs is a factor to be considered, as triangular cross-sectional Fin-FETs have better gate control, higher ON/OFF ratio, and lower OFF current, drain-induced barrier lowering and subthreshold slope, compared to rectangular or bullet shapes. The most successful solution to these problems is coming from the construction of FinFETs, FETs with multiple gates or in which the gate surrounds the nanowires for improved control, [108] as well as vertically stacking them.…”

“…De Marchi et al combined these approaches by fabricating a double gate, gate‐all‐around FET with vertically stacked SiNWs, where one gate electrode configured device polarity (n‐ or p‐type), while the other one could switch it ON and OFF (Figure i). As it was also demonstrated by Seoane et al using nanoscale InGaAs, the cross‐sectional shape in FinFETs is a factor to be considered, as triangular cross‐sectional FinFETs have better gate control, higher ON/OFF ratio, and lower OFF current, drain‐induced barrier lowering and subthreshold slope, compared to rectangular or bullet shapes. The cross section would be expected to influence silicon nanowires as well.…”

A Multi-Method Simulation Toolbox to Study Performance and Variability of Nanowire FETs

“…Several sources of intrinsic device variability are considered in VENDES: i) Metal Grain Granularity (MGG) [39], ii) line edge roughness (LER) [16], iii) gate edge roughness (GER) [7] and iv) random discrete dopants (RD) [40]. These variability sources, together with oxide thickness variations (OTV) and interface trap charges (ITC), were shown to affect FinFETs and GAA-NW FETs the most [5,41].…”

Влияние формы плавника и толщины скрытого оксидного слоя на DIBL-эффект в FinFET-транзисторе, изготовленном по технологии "кремний на изоляторе"

“…Вместе с тем направленные изменения геометрии и структуры транзистора могут улучшить ККЭ. Поэтому с этим в последнее время проводится много исследований, связанных с моделированием влияния параметров наномасштабных МОП-транзисторов на ККЭ, в частности на DIBL-эффект в FinFET-транзисторах [4][5][6][7][8][9]. Так, в работах [4,7] моделировалось влияние расширения стоковых (истоковых) областей на DIBL.…”

“…Показано, что наименьшие ККЭ проявляются для треугольного сечения плавника [5] и при соотношении высоты плавника к ширине, меньшем 3 [6]. Моделируются также более сложные формы плавника [8,9]. В [8] рассматривался транзистор с плавником, нижняя часть которого имеет закругленную поверхность, а верхняя -форму куба, и показано, что транзистор с подправленной формой проявляет заметно меньшие короткоканальные эффекты.…”