Impact of Cache Partitioning on Multi-tasking Real Time Embedded Systems

Bui, B.D.; Caccamo, Marco; Sha, Lui; Martínez, José F.

doi:10.1109/rtcsa.2008.42

Cited by 84 publications

(47 citation statements)

References 10 publications

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“…In [14,6] the authors describe different aspects of accessing shared resources taking into account cache memories. In [14] they deal with interferences at the bus level between cache accesses and I/O peripheral transactions, concluding that these kinds of inferences cause unpredictable behaviors.…”

Section: Related Workmentioning

confidence: 99%

“…They present a theoretical framework able to model the interaction between the CPU and the peripherals accessing the front side bus. In [6] they address the cache partitioning problem (to avoid interference between different cores) as an optimization problem. The solution found by the optimization algorithm identifies the optimal size of each cache partition such that the system worst-case utilization is minimized and real-time schedulability is increased.…”

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Hardware support for WCET analysis of hard real-time multicore systems

Paolieri

Quiñones

Cazorla

et al. 2009

SIGARCH Comput. Archit. News

103

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The increasing demand for new functionalities in current and future hard real-time embedded systems like automotive, avionics and space industries is driving an increase in the performance required in embedded processors. Multicore processors represent a good design solution for such systems due to their high performance, low cost and power consumption characteristics. However, hard real-time embedded systems require time analyzability and current multicore processors are less analyzable than single-core processors due to the interferences between different tasks when accessing shared hardware resources. In this paper we propose a multicore architecture with shared resources that allows the execution of applications with hard real-time and non hard real-time constraints at the same time, providing time analizability for the hard real-time tasks so that they can meet their deadlines. Moreover our architecture proposal provides high-performance for the non hard real-time tasks.

show abstract

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Hardware support for WCET analysis of hard real-time multicore systems

Paolieri

Quiñones

Cazorla

et al. 2009

SIGARCH Comput. Archit. News

103

View full text Add to dashboard Cite

show abstract

“…Liedtke et al used page coloring to provide predictability for uniprocessor real-time systems [Liedtke et al 1997]. Bui et al considered the cache partitioning problem "as an optimization problem whose objective is to minimize the worst-case system utilization under the constraint that the sum of all cache partitions cannot exceed the total cache size" [Bui et al 2008]. The authors proposed a genetic algorithm to solve the optimization problem.…”

Section: Software Index-based Partitioningmentioning

confidence: 99%

“…The work proposed by Liedtke et al was the first to use page coloring, also in the context of uniprocessor real-time systems [Liedtke et al 1997]. Bui et al pro- posed a genetic algorithm to optimize the worst-case system utilization by finding the best cache partitioning assignment for a task set [Bui et al 2008]. Guan et al proposed a cache-aware multicore scheduling algorithm that uses page coloring [Guan et al 2009].…”

Section: Software Index-based Partitioningmentioning

confidence: 99%

A Survey on Cache Management Mechanisms for Real-Time Embedded Systems

et al. 2015

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Multicore processors are being extensively used by real-time systems, mainly because of their demand for increased computing power. However, multicore processors have shared resources that affect the predictability of real-time systems, which is the key to correctly estimate the worst-case execution time of tasks. One of the main factors for unpredictability in a multicore processor is the cache memory hierarchy. Recently, many research works have proposed different techniques to deal with caches in multicore processors in the context of real-time systems. Nevertheless, a review and categorization of these techniques is still an open topic and would be very useful for the real-time community. In this article, we present a survey of cache management techniques for real-time embedded systems, from the first studies of the field in 1990 up to the latest research published in 2014. We categorize the main research works and provide a detailed comparison in terms of similarities and differences. We also identify key challenges and discuss future research directions.

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“…Prior work on soft real-time systems has used static cache partitioning to provide strict QoS [8,28]. In contrast, Ubik manages partition sizes dynamically and at fine granularity to provide QoS to latency-critical workloads, and, at the same time, maximize the space available to batch applications.…”

Section: Cache Management In Real-time Systemsmentioning

confidence: 99%

Ubik

Kasture

Sánchez

2014

Proceedings of the 19th International Conference on Architectural Support for Programming Languages and Operating Systems

114

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Chip-multiprocessors (CMPs) must often execute workload mixes with different performance requirements. On one hand, user-facing, latency-critical applications (e.g., web search) need low tail (i.e., worst-case) latencies, often in the millisecond range, and have inherently low utilization. On the other hand, compute-intensive batch applications (e.g., MapReduce) only need high long-term average performance. In current CMPs, latency-critical and batch applications cannot run concurrently due to interference on shared resources. Unfortunately, prior work on quality of service (QoS) in CMPs has focused on guaranteeing average performance, not tail latency.In this work, we analyze several latency-critical workloads, and show that guaranteeing average performance is insufficient to maintain low tail latency, because microarchitectural resources with state, such as caches or cores, exert inertia on instantaneous workload performance. Last-level caches impart the highest inertia, as workloads take tens of milliseconds to warm them up. When left unmanaged, or when managed with conventional QoS frameworks, shared last-level caches degrade tail latency significantly. Instead, we propose Ubik, a dynamic partitioning technique that predicts and exploits the transient behavior of latency-critical workloads to maintain their tail latency while maximizing the cache space available to batch applications. Using extensive simulations, we show that, while conventional QoS frameworks degrade tail latency by up to 2.3×, Ubik simultaneously maintains the tail latency of latency-critical workloads and significantly improves the performance of batch applications.

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Impact of Cache Partitioning on Multi-tasking Real Time Embedded Systems

Cited by 84 publications

References 10 publications

Hardware support for WCET analysis of hard real-time multicore systems

Hardware support for WCET analysis of hard real-time multicore systems

A Survey on Cache Management Mechanisms for Real-Time Embedded Systems

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