Abstract:a b s t r a c tAs the development of kesterite solar cells accelerates, the bottlenecks in device performance need to be identified and ways for their circumvention defined and developed. In this work, we use 2-dimensional (2D) numerical simulations to explore possible reasons for low open-circuit voltage (V oc ) in Cu 2 (Zn,Sn) Se 4 (CZTSe) solar cells. High defect density in the CZTSe absorber and at the CZTSe/CdS interface can be significant reasons for V oc deficit, but they do not explain all of the losse… Show more
“…This could be a further reason for the observed V oc increase because Cu rich grain boundaries can decrease the bandgap of CZTSe locally which is reported to be detrimental to device performance (V oc ) due to enhanced recombination, as theoretical simulations suggest. 44 This is in line with recent nanoscale investigations of grain boundaries in high performance CZTSSe device where Cu poor grain boundaries are observed after air annealing. 9 However, different to the findings of K. Sardashti et al 9 for CZTSSe absorbers no SnO x could be evidenced in the grain boundaries.…”
A detailed study explaining the beneficial effects of low temperature post deposition annealing combined with selective surface etchings for Cu 2 ZnSnSe 4 (CZTSe) based solar cells is presented. After performing a selective oxidizing surface etching to remove ZnSe secondary phases typically formed during the synthesis processes an additional 200ºC annealing step is necessary to increase device performance from below 3% power conversion efficiency up to 8.3% for the best case. This significant increase in efficiency can be explained by changes in the surface chemistry which results in strong improvement of the CdS/CZTSe heterojunction commonly used in this kind of absorber/buffer/window heterojunction solar cells. XPS measurements reveal that the 200ºC annealing promotes a Cu depletion and Zn enrichment of the etched CZTSe absorber surface relative to the CZTSe bulk. Raman measurements confirm a change in Cu/Zn ordering and increase in defect density. Furthermore, TEM microstructural investigations indicate a change of grain boundaries composition by a reduction of their Cu content after the 200ºC annealing treatment. Additionally, insights in the CdS/CZTSe interface are gained showing a significant amount of Cu in the CdS buffer layer which further helps the formation of a Cu-depleted surface and seems to play an important role in the formation of the pn-heterojunction.
“…This could be a further reason for the observed V oc increase because Cu rich grain boundaries can decrease the bandgap of CZTSe locally which is reported to be detrimental to device performance (V oc ) due to enhanced recombination, as theoretical simulations suggest. 44 This is in line with recent nanoscale investigations of grain boundaries in high performance CZTSSe device where Cu poor grain boundaries are observed after air annealing. 9 However, different to the findings of K. Sardashti et al 9 for CZTSSe absorbers no SnO x could be evidenced in the grain boundaries.…”
A detailed study explaining the beneficial effects of low temperature post deposition annealing combined with selective surface etchings for Cu 2 ZnSnSe 4 (CZTSe) based solar cells is presented. After performing a selective oxidizing surface etching to remove ZnSe secondary phases typically formed during the synthesis processes an additional 200ºC annealing step is necessary to increase device performance from below 3% power conversion efficiency up to 8.3% for the best case. This significant increase in efficiency can be explained by changes in the surface chemistry which results in strong improvement of the CdS/CZTSe heterojunction commonly used in this kind of absorber/buffer/window heterojunction solar cells. XPS measurements reveal that the 200ºC annealing promotes a Cu depletion and Zn enrichment of the etched CZTSe absorber surface relative to the CZTSe bulk. Raman measurements confirm a change in Cu/Zn ordering and increase in defect density. Furthermore, TEM microstructural investigations indicate a change of grain boundaries composition by a reduction of their Cu content after the 200ºC annealing treatment. Additionally, insights in the CdS/CZTSe interface are gained showing a significant amount of Cu in the CdS buffer layer which further helps the formation of a Cu-depleted surface and seems to play an important role in the formation of the pn-heterojunction.
“…All these optimization results give helpful indication for feasible fabrication process. Relative permittivity, ε r 10 13.6 [33] Electron mobility, µ n (cm 2 /V.s) 100 100 [33] Hole mobility, µ p (cm 2 [33] Hole recombination velocity at CdS front surface, S p (cm/s) 10 7 - [35] Electron recombination velocity at CZTSSe back surface, S n (cm/s) -10 7 [35] Defect density, N t (cm -3 ) 1×10 17 1.35×10 15 [34] Electron capture cross section, σ e (cm 2 ) 10 -17 10 -14 [34] Hole capture cross section, σ h (cm 2 ) 10 -13 10 -14 [34] General device properties Reflectivity, R 0.1 [36] Series resistance, R s (Ω-cm 2 ) 0.72 [15] Shunt conductance, G sh (Ω -1 -cm -2 ) = 1/ R sh 1.61×10 -3 [15] Diode ideality factor Q 1.45 [15] Cell temperature, …”
“…Table 1 shows ZnO:Al, ZnO and CdS material parameters used in the simulation which were selected based on experimental values reported on literature and theory. These parameters have been broadly used for modeling CIGS, CdTe and kesterite solar cells [23,25,26,[28][29][30][31]. On the other hand, most CZTS material properties used in the simulation were taken from the electrical and optical characterization results reported for CZTS-based solar cells with record efficiencies [1,32].…”
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