Impact of boron penetration at P/sup +/-poly/gate oxide interface on deep-submicron device reliability for dual-gate CMOS technologies

Oxidation characteristics of nonpatterned and patterned poly-SiGe layers were evaluated to confirm the feasibility for the application of poly-SiGe to the gate electrode. Characterization of poly-SiGe after oxidation was performed using atomic force microscopy ͑AFM͒, X-ray photoelectron spectroscopy ͑XPS͒, cross-sectional transmission electron microscopy ͑TEM͒, and energy-dispersive X-ray spectroscopy ͑EDS͒. The oxide thickness on poly-SiGe layer increased with increasing Ge content, while that on poly-SiGe ͑Ge 20%͒ sample was comparable to that of poly-Si ͑Ge 0%͒. When the Ge content was more than 40%, two different oxide layers were observed on poly-SiGe. Intensive analyses revealed that the oxide layers were composed of SiO 2 -rich mixed oxide (SiO 2 ͑GeO 2 ͒) and GeO 2 -rich mixed oxide (GeO 2 ͑SiO 2 ͒͒. For the patterned poly-SiGe sample, the oxidation characteristics were similar to those of nonpatterned sample. The best sidewall oxide profile was obtained in poly-SiGe ͑Ge 20%͒ sample. Because the sidewall oxide thickness is too thick for poly-SiGe sample with more than 40% of Ge, poly-SiGe ͑Ge 20%͒ is believed to be the most suitable candidate for gate electrode material.

mentioning

confidence: 99%

Effects of Ge Content on the Oxidation Behavior of Poly-Si[sub 1−x]Ge[sub x] Layers for Gate Electrode Application

Ahn¹,

Yeo²,

Kim³

et al. 2001

“…However, at this temperature, boron doped to gate for the surface PMOS can penetrate to the n-well via the gate oxide and thus reduce the threshold voltage of the PMOS. 9 To avoid this problem, we developed an oxidation recipe at 710°C, as mentioned earlier. Figure 3 shows the variation of the threshold voltage of the NMOS and PMOS as a function of gate length at a constant channel width of 10 m. As shown, no short channel effect is observed at the gate length of 0.18 m.…”

Section: Resultsmentioning

confidence: 99%

Compact 1T RAM Cell for System-on-Chip Application

Lee

Lim

Jang

et al. 2005

In this article, a 1T random access memory ͑RAM͒ cell suitable for system-on-chip application is described. The cell consists of a newly developed stack capacitor and an access transistor. The cell size is 0.99 m 2 with 0.18 m logic process. Note that the process is fully compatible with standard logic and requires three additional mask steps for capacitor formation. It is shown that the characteristic of the transistor is not degraded by the added process for capacitor formation. No short channel effects of an n-channel metal oxide semiconductor field effect transistor ͑NMOS͒ and p-channel MOS ͑PMOS͒ are shown up to 0.18 m. The saturation currents of NMOS and PMOS are 600 and 270 A/m, respectively, at 1.8 V operation, and these values are exactly the same as those of the transistor performance fabricated with the standard logic process. Thermal processing is kept below 710°C during stack capacitor formation to prevent boron penetration in the PMOS transistor and to keep the thermal stability of cobalt silicide. The enhanced double stack capacitor structure gives a cell capacitance of 11.5 fF, and the refresh time measured at 1 Mb density exceeds 100 ms. The standby current of a 1 Mb array is about 12 A, which is comparable to that of a six-transistor static RAM cell.

“…As the size of the complementary metal oxide semiconductor ͑CMOS͒ device scales down, conventionally used polycide or salicide gate stack with poly Si films show serious issues of gate depletion effect, boron penetration, and additional effects. [1][2][3] The gate depletion effect causes an increase in total effective oxide thickness, which reduces the inversion capacitance and results in current degradation and boron penetration across the gate oxide leads to threshold voltage instability. 4,5 In addition, while the gate oxide must be scaled as well to control the short channel effect, gate depletion effect and boron penetration are accelerated by the thinner the gate oxide.…”

mentioning

confidence: 99%

Physical and Electrical Properties of Polycrystalline Si[sub 1−x]Ge[sub x] Deposited Using Single-Wafer-Type Low Pressure CVD

Kang

Kim

Min

et al. 2004

Polycrystalline ͑poly͒ Si 1Ϫx Ge x films have been suggested as a promising alternative to the currently employed poly silicon gate electrode for complementary metal oxide semiconductor field effect transistor technology due to lower resistivity, less boron penetration, and less gate depletion effect than that of poly Si gates. We investigated the deposition characteristics and physical properties of poly Si 1Ϫx Ge x films using SiH 4 and GeH 4 as deposition source gases in single-wafer-type low pressure chemical vapor deposition ͑LPCVD͒ system and the electrical properties of P ϩ MOS capacitors with the poly Si 1Ϫx Ge x /45 Å SiO 2 gate stack. Deposition rate as well as Ge content of poly Si 1Ϫx Ge x films shows the large increase with the addition of a small fraction of GeH 4 , while, above critical GeH 4 flux, it is slightly changed. In addition, the Ge content in poly Si 1Ϫx Ge x films decreased with an increase in deposition temperature. The flatband voltage of the poly Si 0.4 Ge 0.6 gate stack decreased by 0.3 V and gate depletion effect of poly Si 0.4 Ge 0.6 gate stack was reduced by 18% as compared to that of the poly Si gate stack. In addition, the charge to breakdown (Q BD ) of the poly Si 0.85 Ge 0.15 gate stack was higher than that of poly Si gate stack.