Impact of advanced patterning options, 193nm and EUV, on local interconnect performance

Abstract

The aim of this paper is to predict the performance of local interconnects, manufactured by advanced patterning options as double patterning and EUV lithography. Electrical wire parameters as resistance, capacitance, RC delay and coupling between adjacent wires are extracted by simulation from scaled 2-D interconnect models, calibrated with dimensions and electrical parameters measured on simple test structures. CD and overlay variations of each patterning option are estimated from experimental and ITRS data and are included in the models. The extracted wire parameters allow the comparison between the patterning options and indicate the optimal choice for the next technology nodes.

Tease

“…To keep performance at pace, devices are evolving from a planar to 3D known as Bulk finFET. To contact devices, Middle of Line inter-metals are introduced, self-aligned, to limit resistance and keep parasitics contained [3].The tight interconnect pitches force the lower and intermediate level BEOL to double patterning such as Litho-Etch-Litho-Etch (LELE) or Self-aligned Double patterning (SADP) and self-aligned Vias. However, each of these innovations result in severe bottlenecks from a circuit design perspective.…”

Comprehensive Performance Analysis of Interconnect Variation by Double and Triple Patterning Lithography Processes

“…However, there are several inherent side effects in multipatterning lithography. The critical dimension (CD), or metal width, or metal height (H) between two adjacent lines (or three parallel lines in TPL) vary as the result of two (or three) separate lithography and etching processes [13]. In addition, overlay (OL) errors occur because of the misalignment between two or three consecutive lithoetch processes [9,14,15].…”

“…The authors showed statistical analysis results in which OL and etch bias were the most important factors in space variability. The performance impact of RC delay and coupling capacitance on local interconnects by several advanced patterning options such as LELE, spacer-defined double patterning (SDDP), and extreme ultraviolet (EUV) lithography were analyzed in [13]. In [14], the process impacts of various DPL strategies were investigated, and the authors proposed a methodology to minimize the OL.…”