Impact of a SADP flow on the design and process for N10/N7 metal layers

Gillijns, Werner; Sherazi, Syed Muhammad Yasser; Trivkovic, Darko; Chava, Bharani; Vandewalle, B.; Gerousis, Vassilios; Raghavan, Praveen; Ryckaert, Julien; Mercha, K.; Verkest, D.; McIntyre, Gregory; Ronse, Kurt G.

doi:10.1117/12.2085923

Cited by 12 publications

(7 citation statements)

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“…This is up to 10-15% in power and performance. Various works like [3,5] Table 1: Impact on power and performance due to full metal fill based routing vs the intent Figure 5, shows wafer cost for a die based on the model introduced in [6]. For both N10 and N7 there is an extra cost that is calculated for the scenario where the pitch of the first two routing layers (M2 and M3) is already relaxed as compared to the layers used to make the standard cell.…”

Section: Metal Pitch Relaxation Advantagesmentioning

confidence: 99%

Metal stack optimization for low-power and high-density for N7-N5

et al. 2016

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One of the key challenges while scaling logic down to N7 and N5 is the requirement of self-aligned multiple patterning for the metal stack. This comes with a large cost of the backend cost and therefore a careful stack optimization is required. Various layers in the stack have different purposes and therefore their choice of pitch and number of layers is critical. Furthermore, when in ultra scaled dimensions of N7 or N5, the number of patterning options are also much larger ranging from multiple LE, EUV to SADP/SAQP. The right choice of these are also needed patterning techniques that use a full grating of wires like SADP/SAQP techniques introduce high level of metal dummies into the design. This implies a large capacitance penalty to the design therefore having large performance and power penalties. This is often mitigated with extra masking strategies. This paper discusses a holistic view of metal stack optimization from standard cell level all the way to routing and the corresponding trade-off that exist for this space. Pitch selection towards N7/N5The figure below shows the range of metal and poly pitches for N7/N5. These two pitch choices determine eventually the chip area. As we scale towards N7/N5, the choice of metal pitch ranges from 36nm down to 20nm. Typical choice of pitches is best aligned next to the limit. This allows to get the most scaling for a given patterning choice. However, for the pitch range for N7 is in the middle multiple patterning options, which makes the choice quite important. Figure 1: Poly Pitch vs Metal pitch choices for N7-N5 Standard cell design and metallization choicesIn the space of N7 all the tight pitch metal layers need to be unidirectional. In this unidirectional scenario the first metal layer is preferred to be perpendicular to the gate. This layer is referred to in our discussion as Mint (intermediate metal) that connects the the Metal 1 that runs parallel to gate at the same pitch as the gate. Mint and M1 metal layers are needed to complete the standard cell. M2 is the 2 nd horizontal metal layer which is also used to finish the standard cell however very limited M2 is needed to complete the standard cell. 90, 80 64, 56 70, 52 45, 40 54, 34 32, 28 42, 22 22, 20 33, 14 16, 14 N10 N7 N5 90, 64 90, 64 78, 64 64, 48 64, 42 64, 42 44, 36 30, 24 20, 18 N10 N7 N5 N3 Mx LE3 cliff Mx SADP cliff Mx SAQP cliff CPP SADP cliff CPP SAQP cliff LI LE3 cliff EUV 1D … Mx LE2 cliff EUV 2D … 10 20 30 40 50 60 70 80 90 10 20 30 40 50 60 70 80 90 100 Metal 2 pitch [ nm ] Contacted Poly Pitch [ nm ]Design-Process-Technology Co-optimization for Manufacturability X, edited by

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Section: Metal Pitch Relaxation Advantagesmentioning

confidence: 99%

Metal stack optimization for low-power and high-density for N7-N5

et al. 2016

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“…In future technology nodes, regular routing patterns towards 1-D gridded design are preferred due to better manufacturability and simplified coloring schemes [45]. The spacer-type MPL is potentially attractive for lower metal routing layers due to its better control on overlay and line edge roughness.…”

Section: Dfm In Routingmentioning

confidence: 99%

Design for manufacturability and reliability in extreme-scaling VLSI

Roy

et al. 2016

Sci. China Inf. Sci.

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In the last five decades, the number of transistors on a chip has increased exponentially in accordance with the Moore's law, and the semiconductor industry has followed this law as long-term planning and targeting for research and development. However, as the transistor feature size is further shrunk to sub-14nm nanometer regime, modern integrated circuit (IC) designs are challenged by exacerbated manufacturability and reliability issues. To overcome these grand challenges, full-chip modeling and physical design tools are imperative to achieve high manufacturability and reliability. In this paper, we will discuss some key process technology and VLSI design co-optimization issues in nanometer VLSI.

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“…As shown in Fig. 12 Post-routing decomposition with line-end extensions, (a) target patterns, (b) 193 nm cut [16], [56], (c) E-beam cut [7], [10], (d) guiding template with DSA cut [61]. Fig.…”

Section: Cut/trim Mask Redistributionmentioning

confidence: 99%

“…In advanced technology nodes, unidirectional line patterns can be manufactured with tight overlay control using selfaligned type of MPL [16], [56]. To obtain target routing patterns, manufacturing-friendly cut/trim mask is designed to remove undesired portions of the lines as illustrated in Fig.…”

Section: Post-routing Optimizationmentioning

confidence: 99%

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Toward Unidirectional Routing Closure in Advanced Technology Nodes

Pan

2017

IPSJ Transactions on System LSI Design Methodology

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Abstract:In advanced technology nodes, unidirectional layout is strongly preferred for high-density metal layers for better manufacturability. The lithography printing of unidirectional layout can be tightly controlled with illumination source optimization and resolution enhancement techniques. Meanwhile, with the unidirectional layout, self-aligned double and quadruple patterning can be applied to achieve finer pitches beyond the resolutions limits of 193 nm lithography tools. However, unidirectional layout style introduces significant impacts on the physical design flow. Notably, unidirectional routing limits the standard cell pin accessibility, which makes manual cell layout design and optimization more and more challenging under modern standard cell architecture. In the routing phase, routing densities and resource competitions on lower metal layers are becoming increasingly high, where intelligent approaches are needed to resolve routing resource competitions for unidirectional routing closure. Moreover, post-routing optimization is inevitable to avoid significant engineering-changing-efforts for unidirectional routing under advanced manufacturing constraints. In this paper, we present a holistic approach, including standard pin access evaluation/optimization, pin access and routing co-optimization and post-routing optimization, to enable unidirectional routing closure in advanced technology nodes.

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Impact of a SADP flow on the design and process for N10/N7 metal layers

Cited by 12 publications

References 0 publications

Metal stack optimization for low-power and high-density for N7-N5

Metal stack optimization for low-power and high-density for N7-N5

Design for manufacturability and reliability in extreme-scaling VLSI

Toward Unidirectional Routing Closure in Advanced Technology Nodes

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