Metal stack optimization for low-power and high-density for N7-N5

Abstract

One of the key challenges while scaling logic down to N7 and N5 is the requirement of self-aligned multiple patterning for the metal stack. This comes with a large cost of the backend cost and therefore a careful stack optimization is required. Various layers in the stack have different purposes and therefore their choice of pitch and number of layers is critical. Furthermore, when in ultra scaled dimensions of N7 or N5, the number of patterning options are also much larger ranging from multiple LE, EUV to SADP/SAQP. The right choice of these are also needed patterning techniques that use a full grating of wires like SADP/SAQP techniques introduce high level of metal dummies into the design. This implies a large capacitance penalty to the design therefore having large performance and power penalties. This is often mitigated with extra masking strategies. This paper discusses a holistic view of metal stack optimization from standard cell level all the way to routing and the corresponding trade-off that exist for this space. Pitch selection towards N7/N5The figure below shows the range of metal and poly pitches for N7/N5. These two pitch choices determine eventually the chip area. As we scale towards N7/N5, the choice of metal pitch ranges from 36nm down to 20nm. Typical choice of pitches is best aligned next to the limit. This allows to get the most scaling for a given patterning choice. However, for the pitch range for N7 is in the middle multiple patterning options, which makes the choice quite important. Figure 1: Poly Pitch vs Metal pitch choices for N7-N5 Standard cell design and metallization choicesIn the space of N7 all the tight pitch metal layers need to be unidirectional. In this unidirectional scenario the first metal layer is preferred to be perpendicular to the gate. This layer is referred to in our discussion as Mint (intermediate metal) that connects the the Metal 1 that runs parallel to gate at the same pitch as the gate. Mint and M1 metal layers are needed to complete the standard cell. M2 is the 2 nd horizontal metal layer which is also used to finish the standard cell however very limited M2 is needed to complete the standard cell. 90, 80 64, 56 70, 52 45, 40 54, 34 32, 28 42, 22 22, 20 33, 14 16, 14 N10 N7 N5 90, 64 90, 64 78, 64 64, 48 64, 42 64, 42 44, 36 30, 24 20, 18 N10 N7 N5 N3 Mx LE3 cliff Mx SADP cliff Mx SAQP cliff CPP SADP cliff CPP SAQP cliff LI LE3 cliff EUV 1D … Mx LE2 cliff EUV 2D … 10 20 30 40 50 60 70 80 90 10 20 30 40 50 60 70 80 90 100 Metal 2 pitch [ nm ] Contacted Poly Pitch [ nm ]Design-Process-Technology Co-optimization for Manufacturability X, edited by

Non-Uniform Temperature Distribution in Interconnects and Its Impact on Electromigration

“…The mean values for the parameters are obtained from recent experimental reports on modern manufacturing processes [4][5][6][7]. This model confirms that for novel technologies [12][13][14][15][16][17], neglecting the temperature evolution and its impact on interconnect reliability and their lifetime may lead to wrong conclusions or catastrophic failures.…”

“…However, the corresponding current and the interconnect width are used appropriately. The mean values for the parameters are obtained from recent experimental reports on modern manufacturing processes of major foundries [4][5][6][7] [13][14][15][16][17]. Due to the space limit, the effects are shown for local interconnects only; similar observations can be made for other layers.…”

“…The segment is then properly constructed in COMSOL Multiphysics [12]. The values for geometrical, electrical, mechanical and thermal properties of technology are obtained from various recent reports of major foundries for 10nm [4][5][6] [13][14][15][16][17]. Via effect which explains the inter-layer heat transfer is also employed for realistic and accurate modeling [1] [9].…”

“…Table 1 shows the application of our model to intermediate-length interconnects in 10nm technology under various thermal profiles (due to Joule heating). The values for geometrical, electrical, mechanical and thermal properties of technology are obtained from [1][2][3] [15][16][17][18][19]. Table 1 present the experiments on two similar wires with lengths of 50um and 100um.…”