Impact of a metal-strip on a polarity-based electrically doped TFET for improvement of DC and analog/RF performance

Chandan, Bandi Venkata; Gautami, Maitreyee; Nigam, Kaushal; Sharma, Dheeraj; Tikkiwal, Vinay Anand; Yadav, Shivendra; Kumar, Satyendra

doi:10.1007/s10825-018-1280-z

Cited by 31 publications

(6 citation statements)

References 32 publications

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“…However, TFETs have been reported some major limitations such as ambipolar current, lower ON-state current (I ON ) and poor analog/radio frequency performance due to inefficient band-to-band tunneling [6]. Therefore, to overcome the lower ONstate current issue, various methods have been reported by the researchers, such as double-gate TFET, workfunction engineering, hetero-dielectric, stacked gate structure, electrically doped (ED), pocket doping, dielectric pocket, Extended Source TFET, dual material and gate over source overlap [6]- [22]. Furthermore, to address the ambipolar current issue, various methods have been reported such as, hetero-dielectric, work-function engineering, stacked gate structure, pocket doping, dual material gate [23]- [25].…”

Section: Introductionmentioning

confidence: 99%

Temperature sensitivity analysis of dual material stack gate oxide source dielectric pocket TFET

2022

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Temperature dependence performance variation is one of the major concerns in predicting the actual electrical characteristics of the device as the bandgap of semiconducting material varies with temperature. Therefore, in this article, for the first time the impact of temperature variations ranging from 300K to 450K on the DC, analog/ radio frequency, and linearity performance of dual material stack gate oxide-source dielectric pocket-tunnel-field-effect transistor (DMSGO-SDP-TFET) is investigated. In this regard, technology computer-aided design (TCAD) simulator is used to analyze DC, and analog/radio frequency performance parameters such as carrier concentration, energy band variation, band-to-band tunneling rate (BTBT), I DS − V GS characteristics, transconductance (g m ), cut off frequency (f T ), gain-bandwidth product (GBP), maximum oscillating frequency (f max ), transconductance frequency product (TFP), and transit time (τ ) considering the impact of temperature variations. Furthermore, linearity parameters such as third-order transconductance (g m3 ), third-order voltage intercept point (VIP3), third-order input-interception point (IIP3), and intermodulation distortion (IMD3) are also analyzed with temperature variations as these performance parameters are significant for linear and analog/radio frequency applications. Moreover, the performance of the proposed DMSGO-SDP-TFET is compared with the conventional dual-material stack gate oxide-tunnel-fieldeffect transistor (DMSGO-TFET). From the comparative analysis, in terms of % per kelvin, DMSGO-SDP-Dharmender (corresponding author)

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Section: Introductionmentioning

confidence: 99%

Temperature sensitivity analysis of dual material stack gate oxide source dielectric pocket TFET

2022

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“…However, ambipolarity and lower ON-state current (I ON ) are two major limitations for TFETs [9]. To address these concerns, researchers proposed various device structures such as double-gate, dual material gate, workfunction engineering, material engineering, stacked gate oxide, pocket doping, electrically doped (ED), dielectric pocket, and gate over source overlap, and extended source TFET [10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28]. In addition to the above issues, the reliability issues that arise as a result of ITCs developed at the Si-SiO 2 interface due to variations in process, stress, radiation, and the effect of hot carriers are also major concerns [32][33][34][35][36][37][38].…”

Section: Introductionmentioning

confidence: 99%

Impact of Interface Trap Charges and Temperature on the Performance of Extended Source Double Gate TFET

Dharmender

Nigam

Kumar

2022

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In this work, we have investigated the reliability of the extended source double gate tunnel field-effect transistor (ESDG-TFET) by considering the effect of the fixed donor (positive) and acceptor (negative) interface trap charges (ITCs) at the silicon-SiO2 interface and temperature variations ranging from 300K to 480K, on the DC, analog/radio frequency (RF), linearity and harmonic distortion performance parameters. A comparative analysis has been performed between conventional stack gate oxide double gate TFET (SGO-DG-TFET) and ESDG-TFET with similar dimensions. Different performance metrics such as transfer characteristics, parasitic capacitances, gain-bandwidth product (GBP), unity gain frequency (fT), transit time, transconductance frequency product (TFP), and linearity distortion performance parameters such as 2nd and 3rd order transconductance coefficients (gm2, gm3), 2nd and 3rd order voltage intercept points (VIP2, VIP3), 3rd order input intercept point, intermodulation distortion parameters (IIP3, IMD3), and 1dB compression point have been investigated. Moreover, 2nd and 3rd order harmonic distortions (HD2, HD3) and total harmonic distortion (THD) are investigated using technology computer-aided design (TCAD) simulations. The Tables 2, 3 and 4 show that in terms of percentage variation, ESDG-TFET exhibits less variation as compared to SGO-DG-TFET, which indicates that the ESDG-TFET is more immune to ITCs and temperature variations. Thus, ESDG-TFET can be used for low power switching and analog/RF and high temperature applications.

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“…The authors have reported I ON /I OF F ratio of (4.5×10 9 ), SS of (48 mV/decade), f T of (1.19 GH Z ). Chandan et al [16] proposed a metal strip based TFET (MS-ED-TFET) to overcome low switching ratio, SS and analog/RF performance and acheived an I ON /I OF F of (8.92×10 8 ), SS of (8.07 mV/decade), g m of 0.007 mS, f T as (0.17 GH Z ). Shaikh et al [17] presented a quadruple-gate TFET with drain engineering (DE-QG-TFET) and acheived an I ON /I OF F ratio of (1.79 ×10 12 ), f T of (∼ 34 GH Z ), g m of 0.261 mS, GBP of (3.9 GH Z ).…”

Section: Introductionmentioning

confidence: 99%

A Novel Approach for Design and Investigation of Dual Material Stack Gate Oxide TFET using Oxide Strip Layer Mechanism

Nigam

Nishad

2021

Preprint

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In this paper, for the first time, we use a distinctive approach based on oxide strip layer in dual material stack gate oxide-tunnel field-effect transistor (DMSGO-OSL-TFET) to improve the DC, analog/RF, and linearity performance. For this, a stack gate oxide with workfunction is considered to enhance the ONstate current (ION ) and reduce the ambipolar current (Iamb). For this case, the gate electrode is tri-segmented, named as tunnel gate (M1), control gate (M2) and auxiliary gate (M3) with different gate lengths (L1, L2, L3) and work functions (φ1, φ2, φ3), respectively. To maintain dual-work functionality, the possible combinations of these work functions are considered. Technology computer-aided design (TCAD) simulations are performed and noted that the workfunction combination (φ1 = φ3 < φ2) outperforms compared to other structures. Where φ1 on the source side is used to enhance the ION , while φ3 (equal to φ1) is used on the drain side to minimize the Iamb. To further enhance the device performance, a high-K oxide strip layer is considered on the drain side to suppress the (Iamb) whereas, a low-K oxide strip layer is used at the source junction to maximize the ION . Moreover, length of gate segments, oxide strip layer height, and thickness are optimized to achieve a better ION , switching ratio, subthreshold swing (SS) and reduce the (Iamb) which helps in the gain of device and design of analog/RF circuits. The proposed device as compared to dual material control gate-oxide strip layer-TFET (DMCG-OSL-TFET) shows improvement in ION /IOF F (∼ 4.23 times), 84 % increase in transconductance (gm), 136 % increase in cut-off frequency (fT ), 126 % increase in gain bandwidth product (GBP), point subthreshold swing (15.8 mV/decade) and other significant improvements in linearity performance parameters such as gm3, VIP3, IIP3, IMD3 making the proposed device useful for low power switching, analog/RF and linearity applications.

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Impact of a metal-strip on a polarity-based electrically doped TFET for improvement of DC and analog/RF performance

Cited by 31 publications

References 32 publications

Temperature sensitivity analysis of dual material stack gate oxide source dielectric pocket TFET

Temperature sensitivity analysis of dual material stack gate oxide source dielectric pocket TFET

Impact of Interface Trap Charges and Temperature on the Performance of Extended Source Double Gate TFET

A Novel Approach for Design and Investigation of Dual Material Stack Gate Oxide TFET using Oxide Strip Layer Mechanism

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