Impact Analysis of NBTI/PBTI on SRAM V<sub>MIN</sub>and Design Techniques for Improved SRAM V<sub>MIN</sub>

Kim, Tony Tae-Hyoung; Kong, Zhi Hui

doi:10.5573/jsts.2013.13.2.87

Cited by 22 publications

(13 citation statements)

References 21 publications

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“…It has been shown that by optimizing the cell design, eg., α ratio of the cell, proper mix of RM vs WM dominated devices and transistor process optimization, the drift can be controlled to a tolerable level [7]. It has also been shown that NBTI has a stronger impact on Vmin than PBTI [4,5]. Consequently, the memory minimum operating voltage (memory Vmin) has been demonstrated to increase over time to compensate the degraded memory static noise margin (SNM) as shown in Fig 6. Literature has also reported memory stability on process corners due to a word-pulse width effect at time-zero [8].…”

Section: Vmin Aging and Rtnmentioning

confidence: 90%

“…There is plenty of published work which discusses the BTI impact on parametric or Vmin drift, including [4,5]. However, details regarding comprehensive protection against Vmin failures are very limited.…”

Section: Introductionmentioning

confidence: 98%

“…This is especially true for SRAM due to shrinking headroom and rising Vmin. The impact of memory bit cell density and its Vmin trade-off is significant and the risk needs to be mitigated.There is plenty of published work which discusses the BTI impact on parametric or Vmin drift, including [4,5]. However, details regarding comprehensive protection against Vmin failures are very limited.…”

mentioning

confidence: 98%

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Protecting against emerging vmin failures in advanced technology nodes

Lee

Haggag²,

Eklow

2014

2014 International Test Conference

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As technology and voltage scale, both intrinsic and extrinsic Vmin failures can occur at a significant rate. These failures can impact yield and reliability. We propose a novel guardband and advanced outlier limits (AOL) methodology to protect against intrinsic and extrinsic Vmin failures. This paper will demonstrate the impact of aging, RTN and HKMG process variation on Vmin. The data will be used to establish guardbands and AOL to minimize failures during testing and in the field. IntroductionTechnology advancements in Big Data and the data center are putting pressure on memory suppliers to deliver much more memory in smaller packages with lower power and higher reliability. In order to meet these requirements, memory suppliers are pushing the operating voltages closer and closer to Vmin (the minimum voltage level at which a part will reliably operate). The operating margins with respect to Vmin are therefore becoming tighter, and increasing the likelihood of failures. This increase in failure rate is in addition to the failures that naturally occur based on the sheer amount of memory in the data center.As a consequence of technology scaling, process variations, aging, RTN (Random Telegraph Noise), which increases device V t, has become a dominant mechanism degrading device maximum operating frequency (F max ) and minimum operating voltage (V min ). For a device with overdrive (V dd -V t ), an increase in V t requires an increase in minimum V dd to maintain same overdrive, hence V min shift is proportional to V t shift [1]. Vmin is a risk indicator that is based on potential conditions described above.Furthermore to enable higher performance at lower voltage and lower leakage levels, the transistor gate oxide has moved from silicon oxynitride / poly gate (SiON/Poly) to high-k / metal gate (HKMG) which further has reduced intrinsic reliability margin [2]; requiring more novel guard banding and screening techniques for reliability.Complicating matters even further, memory content has doubled for each technology generation which compounds the challenges faced by shrinking memory cells. In deeply scaled technologies, local Vt fluctuations, BTI and RTN are the three biggest issues [3] impacting the margin between the operating supply voltage (Vdd) and the minimum supply voltage below which an SRAM cell cannot be operated (Vmin). Scaling to 0.5X SRAM cell size constant Vmin becomes difficult. Since Vt cannot be scaled down aggressively, due to short channel effect, power-supply voltage (Vdd) has not been scaled down in proportion to the MOSFET channel length. This is especially true for SRAM due to shrinking headroom and rising Vmin. The impact of memory bit cell density and its Vmin trade-off is significant and the risk needs to be mitigated.There is plenty of published work which discusses the BTI impact on parametric or Vmin drift, including [4,5]. However, details regarding comprehensive protection against Vmin failures are very limited. In this paper, we present a methodology to analyze the various contributions...

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Section: Vmin Aging and Rtnmentioning

confidence: 90%

Section: Introductionmentioning

confidence: 98%

mentioning

confidence: 98%

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Protecting against emerging vmin failures in advanced technology nodes

Lee

Haggag²,

Eklow

2014

2014 International Test Conference

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“…Therefore, the stress condition is removed and decreased the threshold voltage. The threshold voltage shift of MOSFET transistors due to BTI effects under static stress can be described by dc reaction and diffusion (R-D) model [2,14,18,21,22,31,32]. If the gate voltage of transistor is regularly flipped under alternative stress, the dc R-D model should be modified to an ac R-D model:…”

Section: Nbti and Pbti Modelsmentioning

confidence: 99%

“…In [1] based on the R-D model some α values are presented to simplify the calculation of the AC degradation factor in terms of the signal probability (Table 1). In [1,21,22,32,33], similar approach is used to incorporate the impact of signal probability in analysis. Fig.…”

Section: Nbti and Pbti Modelsmentioning

confidence: 99%

Adaptive Technique for Overcoming Performance Degradation Due to Aging on 6T SRAM Cells

Faraji

Naji

2014

IEEE Trans. Device Mater. Relib.

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The threshold voltage drifts induced by Positive Bias Temperature Instability (PBTI) and Negative Bias Temperature Instability (NBTI) weaken NMOS and PMOS, respectively. These long-term aging threshold voltage drifts degrade SRAM cell stability, margin and performance. This paper presents a low area overhead Adaptive Body Bias (ABB) circuit that compensates BTI aging effects and also improves performance of an aged SRAM cell. The proposed circuit uses a control circuit and word line voltage to control the voltage applied to the body of 6T SRAM cell's transistors such that the BTI effect dependency of threshold voltage is reduced. In the worst case, the proposed ABB reduces the HOLD SNM degradation by 6.85%, READ SNM degradation by 12.24%, WRITE margin degradation by 2.16%, READ delay by 28.68% and WRITE delay by 32.61% compared to the conventional SRAM cell at 10 8 seconds aging time.

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Enabling efficient rate and temporal coding using reliability‐aware design of a neuromorphic circuit

Picardo

Shaik

Singhal

et al. 2022

Circuit Theory & Apps

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Reliability aspects such as bias temperature instability (BTI) and hot carrier injection (HCI) affecting devices in advanced CMOS-based technology have been the subject of active research in recent decades. Due to these reliability issues, various digital and analog circuits were investigated for degradation.However, circuit blocks like the neuron circuits of neuromorphic systems are not fully explored. This work is inclined toward examining the collective degradation impact of BTI and HCI due to aging in an adaptive exponential "integrate and fire" (I&F) model-based, neuromorphic neuron circuit. Detailed degradation analysis of the stimulated neuron circuit aided in identifying possible mismatches/faults associated with neuron spikes. These factors could reduce the efficiency of the neuronal circuit by potentially affecting the transmission of information in a neuromorphic system. Various performance parameters were then derived to quantify the extent of circuit deterioration. The proposed reliability-aware design aims to improve the circuit degradation through its effectiveness in alleviating the overall reliability impact. It demonstrates enhanced circuit operation in spike generation even after aging. The circuit performance is validated through simulations at "Time0" (pre-degradation) and "Aged" (post-degradation) neuron netlists, which is then compared with the proposed reliability-aware circuit.

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Impact Analysis of NBTI/PBTI on SRAM V_MINand Design Techniques for Improved SRAM V_MIN

Cited by 22 publications

References 21 publications

Protecting against emerging vmin failures in advanced technology nodes

Protecting against emerging vmin failures in advanced technology nodes

Adaptive Technique for Overcoming Performance Degradation Due to Aging on 6T SRAM Cells

Enabling efficient rate and temporal coding using reliability‐aware design of a neuromorphic circuit

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Impact Analysis of NBTI/PBTI on SRAM VMINand Design Techniques for Improved SRAM VMIN

Cited by 22 publications

References 21 publications

Protecting against emerging vmin failures in advanced technology nodes

Protecting against emerging vmin failures in advanced technology nodes

Adaptive Technique for Overcoming Performance Degradation Due to Aging on 6T SRAM Cells

Enabling efficient rate and temporal coding using reliability‐aware design of a neuromorphic circuit

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Impact Analysis of NBTI/PBTI on SRAM V_MINand Design Techniques for Improved SRAM V_MIN