Immersion Lithography Ready for 45 nm Manufacturing and Beyond

Abstract

Enhanced resolution capability, defined in Rayleigh's criterion as:Where R = minimum resolution, λ = exposure wavelength, and k 1 = process dependent factor is the key motivation for the transition to immersion lithography, and the continued push for higher numerical apertures (NA). Regardless of the imaging enhancements made possible by immersion lithography though, this technology would not have been implemented in volume manufacturing if two potential showstoppers identified early on, overlay and defectivity performance, were not successfully overcome.Fortunately, intense collaboration between scanner and track suppliers, resist vendors, and IC manufacturers has yielded significant progress in the critical areas of immersion defectivity and overlay. As a result, immersion lithography is experiencing rapid adoption into mainstream semiconductor manufacturing. Hyper-NA immersion scanners, such as the Nikon NSR-S609B (NA=1.07), began shipping in early 2006 for use in 55 nm production and 45 nm process development. These systems are already being used successfully for 56 nm NAND flash manufacturing. Aggressive industry integration continues, and scanners such as the NSR-S610C (NA=1.30) are fully capable of delivering the critical performance metrics required for 45 nm half-pitch production and beyond. Current areas of industry investigation now focus on the feasibility and practicality of extending immersion lithography to 32 nm applications using new lens and resist materials, as well as exploring alternative immersion fluids to push immersion lithography as far as possible.

Physically-Aware Analysis of Systematic Defects in Integrated Circuits

“…Unfortunately, sub-wavelength lithography results in severe distortions of the layout patterns [1] due to optical diffraction and interference. Many innovative techniques have been developed to reduce/compensate for these distortions that include, for example, optical proximity correction (OPC) [2], phase-shift mask (PSM) [3], immersion lithography [4], and double-patterning [5]. OPC modifies the geometric features in the design layout itself in order to compensate for the distortions.…”

16-Gigabit, 8-level NAND flash memory with 51nm 44-cell string technology

“…Several scaling down technology such as double patterning [1], immersion photo lithography [2] and new device structure with low resistance gate stack [3], high-k material [4] and charge trap devices [5] are considered for the next flash memory era. However scaling-down requires high cost lithography process, and the conventional floating gate has some limitation to be overcome [4].…”