Imitation Learning for Dynamic VFI Control in Large-Scale Manycore Systems

Kim, Ryan; Choi, Wonje; Chen, Zhuo; Doppa, Janardhan Rao; Pande, Partha Pratim; Marculescu, Diana; Mărculescu, Radu

doi:10.1109/tvlsi.2017.2700726

Cited by 48 publications

(42 citation statements)

References 34 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The proposed self-learning decision making mechanism reduces packet latency, which results in improved NoC throughput. [32] proposed an imitation learning (IL) based methodology for dynamic V/F island (cluster of nodes/links) control in manycore systems. [28] presented an NN-based intelligent hotspot prediction mechanism that was used with a congestion-control mechanism to handle hotspot formations efficiently.…”

Section: Background and Prior Workmentioning

confidence: 99%

Reinforcement Learning Enabled Routing for High-Performance Networks-on-Chip

Reza

Le²

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

Network-on-chip (NoC) has been the standard fabric for multi-core architectures. With the increase in cores in the multi-core architectures, the probability of congestion increases because of longer path among sources and destinations in the NoC and because of the presence of multiple applications in a chip. Congestion hampers system performance because of the delay in packet delivery, which in turn results in reduced effective utilization of resources and reduced throughout. Higher congestion also results in higher energy consumption in NoC as packets spend more time in the network. Reactive detection and/or a single fixed routing algorithm are not effective to prevent congestion from happening for different traffic patterns in NoC. Therefore, we propose reinforcement learning based proactive routing technique that selects the best routing algorithm from multiple available routing algorithms using NoC utilization and congestion information to improve communication performance. Simulation results demonstrate latency performance improvement while providing robust NoC performance for different NoC states and traffic demands.

show abstract

Section: Background and Prior Workmentioning

confidence: 99%

Reinforcement Learning Enabled Routing for High-Performance Networks-on-Chip

Reza

Le²

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

show abstract

“…An Q-learning based algorithm was proposed in [61] to identify V/F pairs for predicted workloads and given application performance requirements. The study in [62] investigated imitation learning and reported higher quality policies in the context of dynamic VFI control in many core systems with different applications running concurrently.…”

Section: Reinforcement Learning (Rl)mentioning

confidence: 99%

A Survey of Prediction and Classification Techniques in Multicore Processor Systems

Ababei

Moghaddam

2019

IEEE Trans. Parallel Distrib. Syst.

View full text Add to dashboard Cite

show abstract

“…Kim et al [33] presented an imitation learning (IL) vs. reinforcement learning (RL) comparison to improve the efficiency of dynamic voltage and frequency scaling of voltage islands in a manycore platform. The authors used a combination of gem5 [15] and McPAT [32] as a platform to carry out the experiments.…”

Section: Related Workmentioning

confidence: 99%

Energy Optimization for Large-Scale 3D Manycores in the Dark-Silicon Era

et al. 2019

View full text Add to dashboard Cite

In this paper, we study the impact of the idle/dynamic power consumption ratio on the effectiveness of a multi-V dd /frequency manycore design. We propose a new tool called LVSiM (a Low-Power and Variation-Aware Manycore Simulator) to carry out the experiments. It is a novel manycore simulator targeted towards low-power optimization methods including within-die process and workload variations. LVSiM provides a holistic platform for multi-V dd /frequency voltage island analysis, optimization, and design. It provides a tool for the early design exploration stage to analyze large-scale manycores with a given number of cores on 3D-stacked layers, network-on-chip communication busses, technology parameters, voltage and frequency values, and power grid parameters, using a variety of different optimization methods. LVSiM has been calibrated with Sniper/McPAT at a nominal frequency, and then the energy-delay-product (EDP) numbers were compared after frequency scaling. The average error is shown to be 10% after frequency scaling, which is sufficient for our purposes. The experiments in this work are carried out for different Idle/Dynamic ratios considering 1260 benchmarks with task sizes ranging from 4000 to 16 000 executing on 3200 cores. The best configurations are shown to produce on average 20.7% to 24.6% EDP savings compared to the nominal configuration. Traditional scheduling methods are used in the nominal configuration with the unused cores switched off. In addition, we show that, as the Idle/Dynamic ratio increases, the multi-V dd /frequency approach becomes less effective. In the case of a high Idle/Dynamic ratio, the minimum EDP can be achieved through switching off unused cores as opposed to using a multi-V dd /frequency approach. This conclusion is important, especially in the dark-silicon era, where switching cores on and/or off as needed is a common practice.

show abstract

Imitation Learning for Dynamic VFI Control in Large-Scale Manycore Systems

Cited by 48 publications

References 34 publications

Reinforcement Learning Enabled Routing for High-Performance Networks-on-Chip

Reinforcement Learning Enabled Routing for High-Performance Networks-on-Chip

A Survey of Prediction and Classification Techniques in Multicore Processor Systems

Energy Optimization for Large-Scale 3D Manycores in the Dark-Silicon Era

Contact Info

Product

Resources

About