2021
DOI: 10.1109/tcsi.2021.3063183
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Imbalance-Tolerant Bit-Line Sense Amplifier for Dummy-Less Open Bit-Line Scheme in DRAM

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Cited by 2 publications
(1 citation statement)
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“…The bitline nodes at the IO interface can transfer the amplified voltage to the IO bus or be driven by the write drivers with the help of IO transistors. Isolation transistors are only placed in a folded array structure to isolate SAs from different arrays for reuse [20,21]. Based on the conventional sensing circuit, a low power single bitline write (SBW) sensing circuit with reconfigurable I/O interface was also proposed [22,23].…”
Section: Introductionmentioning
confidence: 99%
“…The bitline nodes at the IO interface can transfer the amplified voltage to the IO bus or be driven by the write drivers with the help of IO transistors. Isolation transistors are only placed in a folded array structure to isolate SAs from different arrays for reuse [20,21]. Based on the conventional sensing circuit, a low power single bitline write (SBW) sensing circuit with reconfigurable I/O interface was also proposed [22,23].…”
Section: Introductionmentioning
confidence: 99%