Image processor capable of block-noise-free JPEG2000 compression with 30 frames/s for digital camera applications

Yamauchi, Hironori; Okada, S.; Taketa, K.; Ohyama, Tatsushi; Matsuda, Yoshihisa; Mori, Takeshi; Watanabe, Takanori; Matsuo, Yasutaka; Yamada, Yasuhiro; Ichikawa, Tadao; Matsushita, Y.

doi:10.1109/isscc.2003.1234201

Cited by 30 publications

(19 citation statements)

References 1 publication

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“…Different from other implementations using quantization method such as [10], the proposed architecture adopts the truncation method in order to obtain three targets: 1)…”

Section: B the Experimental Results And Fpga Verification Of Ebcot Amentioning

confidence: 99%

“…These three targets are achieved at a sacrifice of the amount of computational efforts which put impedance on high throughput, for example, the throughput of this encoder (5.3Mbits/(MHz·s)) is a bit lower than H. Yamauchi [10] (720*480*16*30/27=6.1Mbits/(MHz·s)). However, compared with quantization method which reduces the entropy of wavelet coefficients before AE, implicit quantization adopted by this architecture leaves much more details and room for truncation to control the quality.…”

Section: B the Experimental Results And Fpga Verification Of Ebcot Amentioning

confidence: 99%

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A VLSI architecture of JPEG2000 encoder

Liu

Chen

Meng

et al. 2004

IEEE J. Solid-State Circuits

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Abstract-This paper proposes a VLSI architecture of JPEG2000 encoder, which functionally consists of two parts: Discrete Wavelet Transform (DWT) and Embedded Block Coding with Optimized Truncation (EBCOT). For DWT, a Spatial Combinative Lifting Algorithm (SCLA) based scheme with both 5/3 reversible and 9/7 irreversible filters is adopted to reduce 50% and 42% multiplication computations respectively compared with the conventional Lifting Based Implementation (LBI). For EBCOT, a Dynamic Memory Control (DMC) strategy of Tier-1 encoding is adopted to reduce 60% scale of the on-chip wavelet coefficient storage and a subband parallel-processing method is employed to speed-up the EBCOT Context Formation (CF) process; an architecture of Tier-2 encoding is presented to reduce the scale of on-chip bit-stream buffering from full-tile size down to three-code-block size and considerably eliminate the iterations of the Rate-Distortion (RD) truncation.

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“…Different from other implementations using quantization method such as [10], the proposed architecture adopts the truncation method in order to obtain three targets: 1)…”

Section: B the Experimental Results And Fpga Verification Of Ebcot Amentioning

confidence: 99%

Section: B the Experimental Results And Fpga Verification Of Ebcot Amentioning

confidence: 99%

A VLSI architecture of JPEG2000 encoder

Liu

Chen

Meng

et al. 2004

IEEE J. Solid-State Circuits

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show abstract

“…Instead, we can retransmit the required data at the block boundary from the frame memory. The block-based scheme in [12] is generalized to the overlapped block-based scan method, as shown in Fig. 10(b), where .…”

Section: ) Nonoverlappedmentioning

confidence: 99%

Analysis and VLSI architecture for 1-D and 2-D discrete wavelet transform

Huang

Tseng

Chen

2005

IEEE Trans. Signal Process.

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“…Instead, we can retransmit the required data at the block boundary from the frame memory. The block-based scheme in [9] is generalized to the overlapped block-based scan method as shown in Fig. 1(b), where…”

Section: Non-overlapped and Overlapped Block-based Scanmentioning

confidence: 99%

“…However, the internal buffer would occupy much die area. Many 2-D DWT architectures using different memory structures have been proposed [6,7,8,9,10]. In this paper, we discuss two independent issues of the 2-D DWT architectures.…”

Section: Introductionmentioning

confidence: 99%

Memory analysis and architecture for two-dimensional discrete wavelet transform

Huang

Tseng

Chen

2004 IEEE International Conference on Acoustics, Speech, and Signal Processing

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The large amount of the frame memory access and the die area occupied by the embedded internal buffer are the most critical issues for the implementation of two-dimensional discrete wavelet transform (2-D DWT). The former would consume the most power and waste the system memory bandwidth. The latter would enlarge the chip size and also consume much power. In this paper, we categorize and analyze the 2-D DWT architectures by different external memory scan methods. Then the overlapped stripebased scan method is proposed to provide an efficient and flexible implementation for 2-D DWT. The implementation issues of the internal buffer are also discussed, including the lifting-based and convolution-based. Some real-life experiments are given to show that the performance of area and power for the internal buffer is highly related to memory technology and working frequency, instead of the required memory bits only.

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Image processor capable of block-noise-free JPEG2000 compression with 30 frames/s for digital camera applications

Cited by 30 publications

References 1 publication

A VLSI architecture of JPEG2000 encoder

A VLSI architecture of JPEG2000 encoder

Analysis and VLSI architecture for 1-D and 2-D discrete wavelet transform

Memory analysis and architecture for two-dimensional discrete wavelet transform

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