ILP formulations for variation/defect-tolerant logic mapping on crossbar nano-architectures

Zamani, Morteza Saheb; Mirzaei, Hanieh; Tahoori, Mehdi B.

doi:10.1145/2491680

Cited by 12 publications

(21 citation statements)

References 25 publications

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“…For further evaluations, we also consider different distributions including Weibull, exponential, and Beta distributions. We mainly use COV values of 0.2 that is a common practice in the literature [23], [17], and [15], also supported by the reports of "International Technology Roadmap for Semiconductors (ITRS)" [28] and [29]. We also try different COV values between 0 and 0.3.…”

Section: Resultsmentioning

confidence: 99%

“…On the other hand, our algorithm is designed to make a continuous progress; that is why we call it a hill climbing algorithm. Another approach based on linear integer programming is proposed by Zamani et al [15]. Although satisfactory delay results can be achieved by this systematic method, runtime values are even worse than those of the simulated annealing algorithm.…”

Section: Previous Workmentioning

confidence: 99%

“…After the size of only 8 × 8, it is not feasible to use an exhaustive search. Indeed this problem, commonly known as variation tolerant logic mapping (VTLM) problem, is an NP-Complete problem [15].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays

Peker

Altun

2018

IEEE Trans. Multi-Scale Comp. Syst.

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Nano-crossbar arrays are area and power efficient structures, generally realized with self-assembly based bottom-up fabrication methods as opposed to relatively costly traditional top-down lithography techniques. This advantage comes with a price: very high process variations. In this work, we focus on the worst-case delay optimization problem in the presence of high process variations. As a variation tolerant logic mapping scheme, a fast hill climbing algorithm is proposed; it offers similar or better delay improvements with much smaller runtimes compared to the methods in the literature. Our algorithm first performs a reducing operation for the crossbar motivated by the fact that the whole crossbar is not necessarily needed for the problem. This significantly decreases the computational load up to 72% percent for benchmark functions. Next, initial column mapping is applied. After the first two steps that can be considered as preparatory, the algorithm proceeds to the last step of hill climbing row search with column reordering where optimization for variation tolerance is performed. As an extension to this work, we directly apply our hill climbing algorithm on defective arrays to perform both defect and variation tolerance. Again, simulation results approve the speed of our algorithm, up to 600 times higher compared to the related algorithms in the literature without sacrificing defect and variation tolerance performance.

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Section: Resultsmentioning

confidence: 99%

Section: Previous Workmentioning

confidence: 99%

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A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays

Peker

Altun

2018

IEEE Trans. Multi-Scale Comp. Syst.

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“…The SA method has good effort on variation tolerance, but its efficiency is poor due to the huge search space. Recently, a set of integer linear programming (ILP) formulations were introduced in [17], but the ILP-based method has good results only on small-scale problems.…”

Section: Take Down Policymentioning

confidence: 99%

Defect- and Variation-Tolerant Logic Mapping in Nanocrossbar Using Bipartite Matching and Memetic Algorithm

Yuan

Chen

et al. 2016

IEEE Trans. VLSI Syst.

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High defect density and extreme parameter variation make it very difficult to implement reliable logic functions in crossbar-based nanoarchitectures. It is a major design challenge to tolerate defects and variations simultaneously for such architectures. In this paper, a method based on a bipartite matching and memetic algorithm is proposed for defect-and variation-tolerant logic mapping (D/VTLM) problem in crossbarbased nanoarchitectures. In the proposed method, the search space of the D/VTLM problem can be dramatically reduced through the introduction of the min-max weight maximumbipartite-matching (MMW-MBM) and a related heuristic bipartite matching method. MMW-MBM is defined on a weighted bipartite graph as an MBM, where the maximal weight of the edges in the matching has a minimal value. In addition, a defect-and variation-aware local search (D/VALS) operator is proposed for D/VTLM and embedded in a global search framework. The D/VALS operator is able to utilize the domain knowledge extracted from problem instances and, thus, has the potential to search the solution space more efficiently. Compared with the state-of-the-art heuristic and recursive algorithms, and a simulated annealing algorithm, the good performance of our proposed method is verified on a 3-bit adder and a large set of random benchmarks of various scales.

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“…One disadvantage of this method is that it does not fit for multi-output two-level nanoscale crossbars, such as AND-OR logics. Work in [31] formulated the variation and defect-aware logic mapping problem using a set of integer linear programming. However, the order of complexity of the variables and the constraints of these formulations are high and are not efficient for large-scale circuits.…”

Section: Previous Workmentioning

confidence: 99%

Joint defect- and variation-aware logic mapping of multi-outputs crossbar-based nanoarchitectures

Ghavami

2016

J Comput Electron

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Nanotechnology-based manufacturing, relying on self-assembly of nanotubes or nanowires, has shown promising potentials for future nanoscale circuit designs. However, high defect density and extreme process variations for crossbar-based nanoarchitectures are expected to be fundamental design challenges. Consequently, defect and variation issues must be considered in logic mapping on nanoscale crossbars. In this paper, we establish a mathematical model for the simultaneous variation and defect-aware logic mapping of multi-outputs crossbar arrays. We model this problem using a new sub-weighted-graph isomorphism problem and propose a greedy algorithm for the variation-and defectaware logic mapping. Based on Monte-Carlo simulation, we compare the proposed technique with other logic mapping techniques such as, variation-unaware and exhaustive search mapping in terms of accuracy as well as runtime. Results show that the effectiveness of our new mapping technique in variation and defect tolerance as well as run time improvement.

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ILP formulations for variation/defect-tolerant logic mapping on crossbar nano-architectures

Cited by 12 publications

References 25 publications

A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays

A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays

Defect- and Variation-Tolerant Logic Mapping in Nanocrossbar Using Bipartite Matching and Memetic Algorithm

Joint defect- and variation-aware logic mapping of multi-outputs crossbar-based nanoarchitectures

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