ILA-MCM: Integrating Memory Consistency Models with Instruction-Level Abstractions for Heterogeneous System-on-Chip Verification

Zhang, Hongce; Trippel, Caroline; Manerkar, Yatin A.; Gupta, Aarti; Martonosi, Margaret; Malik, Sharad

doi:10.23919/fmcad.2018.8603015

Cited by 10 publications

(6 citation statements)

References 24 publications

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“…This allows the user to choose the mode of modeling most appropriate to each constraint. For example, the ILA-MCM work [45] combined operational ILA (Instruction Level Abstraction) models to describe the functional behavior of processing elements with memory consistency model (MCM) orderings that are more naturally specified axiomatically [3]. (MCM orderings constrain shared-memory communication and synchronization between multiple processing elements.)…”

Section: Multi-modal Modelingmentioning

confidence: 99%

UCLID5: Multi-Modal Formal Modeling, Verification, and Synthesis

Polgreen¹,

Cheang²,

Gaddamadugu³

et al. 2022

Preprint

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UCLID5 is a tool for the multi-modal formal modeling, verification, and synthesis of systems. It enables one to tackle verification problems for heterogeneous systems such as combinations of hardware and software, or those that have multiple, varied specifications, or systems that require hybrid modes of modeling. A novel aspect of UCLID5 is an emphasis on the use of syntax-guided and inductive synthesis to automate steps in modeling and verification. This tool paper presents new developments in the UCLID5 tool including new language features, integration with new techniques for syntax-guided synthesis and satisfiability solving, support for hyperproperties and combinations of axiomatic and operational modeling, demonstrations on new problem classes, and a robust implementation.

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Section: Multi-modal Modelingmentioning

confidence: 99%

UCLID5: Multi-Modal Formal Modeling, Verification, and Synthesis

Polgreen¹,

Cheang²,

Gaddamadugu³

et al. 2022

Preprint

Self Cite

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“…When integrated with axiomatic memory consistency models that specify orderings between memory operations, the transition relation defined in ILAs (Sect. 2.3) can be used to reason about concurrent interactions between heterogeneous components [8].…”

Section: Other Ilang Applicationsmentioning

confidence: 99%

“…It also enables firmware/hardware co-verification [3]. Further, it enables reasoning about memory consistency models for system-wide properties [8].…”

Section: Introductionmentioning

confidence: 99%

ILAng: A Modeling and Verification Platform for SoCs Using Instruction-Level Abstractions

Huang

Zhang

Gupta

et al. 2019

Tools and Algorithms for the Construction and Analysis of Systems

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We present ILAng, a platform for modeling and verification of systems-on-chip (SoCs) using Instruction-Level Abstractions (ILA). The ILA formal model targeting the hardware-software interface enables a clean separation of concerns between software and hardware through a unified model for heterogeneous processors and accelerators. Topdown it provides a specification for functional verification of hardware, and bottom-up it provides an abstraction for software/hardware coverification. ILAng provides a programming interface for (i) constructing ILA models (ii) synthesizing ILA models from templates using program synthesis techniques (iii) verifying properties on ILA models (iv) behavioral equivalence checking between different ILA models, and between an ILA specification and an implementation. It also provides for translating models and properties into various languages (e.g., Verilog and SMT LIB2) for different verification settings and use of third-party verification tools. This paper demonstrates selected capabilities of the platform through case studies. Data or code related to this paper is available at: [9].

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“…Research and industry practice for relaxed memory semantics rely on making the semantics executable as a test oracle: not just a paper definition (in prose or mathematics), but tool-supported definitions that for small litmus-test examples can compute the set of all allowed executions, that can then be compared against experimental data. Many tools have been developed for operational and axiomatic architectural concurrency models [4,6,8,12,14,[17][18][19][20]25,26,[28][29][30][31][32], with axiomatic tools notably including the Herd tool of Alglave and Maranget [4,6,8], that can evaluate litmus tests w.r.t. axiomatic memory models specified in a relational-algebra style in the Cat language [2].…”

Section: Introductionmentioning

confidence: 99%

“…However, all of these previous tools for axiomatic models have (at best) used hard-coded ISA semantics that cover only small fragments of the complete architecture. For example, Zhang et al [32] use a SMT solver based approach for SoC verification, with a user-specified memory model (TSO or SC), however the instruction level abstractions (ILAs) they use are much more abstract than the ISA semantics we consider.…”

Section: Introductionmentioning

confidence: 99%

Isla: Integrating Full-Scale ISA Semantics and Axiomatic Concurrency Models

Armstrong,

Campbell,

Simner

et al. 2021

Computer Aided Verification

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Architecture specifications such as Armv8-A and RISC-V are the ultimate foundation for software verification and the correctness criteria for hardware verification. They should define the allowed sequential and relaxed-memory concurrency behaviour of programs, but hitherto there has been no integration of full-scale instruction-set architecture (ISA) semantics with axiomatic concurrency models, either in mathematics or in tools. These ISA semantics can be surprisingly large and intricate, e.g. 100k+ lines for Armv8-A. In this paper we present a tool, Isla, for computing the allowed behaviours of concurrent litmus tests with respect to full-scale ISA definitions, in Sail, and arbitrary axiomatic relaxed-memory concurrency models, in the Cat language. It is based on a generic symbolic engine for Sail ISA specifications, which should be valuable also for other verification tasks. We equip the tool with a web interface to make it widely accessible, and illustrate and evaluate it for Armv8-A and RISC-V. By using full-scale and authoritative ISA semantics, this lets one evaluate litmus tests using arbitrary user instructions with high confidence. Moreover, because these ISA specifications give detailed and validated definitions of the sequential aspects of systems functionality, as used by hypervisors and operating systems, e.g. instruction fetch, exceptions, and address translation, our tool provides a basis for developing concurrency semantics for these. We demonstrate this for the Armv8-A instruction-fetch model and self-modifying code examples of Simner et al.

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ILA-MCM: Integrating Memory Consistency Models with Instruction-Level Abstractions for Heterogeneous System-on-Chip Verification

Cited by 10 publications

References 24 publications

UCLID5: Multi-Modal Formal Modeling, Verification, and Synthesis

UCLID5: Multi-Modal Formal Modeling, Verification, and Synthesis

ILAng: A Modeling and Verification Platform for SoCs Using Instruction-Level Abstractions

Isla: Integrating Full-Scale ISA Semantics and Axiomatic Concurrency Models

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