III-N heterostructure devices for low-power logic

Fay, Patrick; Li, W.; Digiovanni, D.; Cao, Lina; Ilatikhameneh, Hesameddin; Chen, F.; Ameen, Tarek A.; Rahman, Rajib; Klimeck, Gerhard; Lund, Cory; Keller, S.; Islam, S. M.; Chaney, Alexander; Cho, Y.; Jena, Debdeep

doi:10.1109/cstic.2017.7919743

Cited by 3 publications

(2 citation statements)

References 6 publications

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“…Tunneling Field Effect Transistors (TFETs) have been one the major device candidates for reducing the supply voltage V DD and power consumption since they can overcome the thermionic limitation of sub-threshold swing (SS) [1]- [3]. The low ON current issue of TFETs has been shown to have several solutions such as III-V [4]- [6], 2D materials [7]- [16] and vertical tunnel field effect transistors (v-TFETs) based on tunneling through vertically stacked heterojunctions [17]- [23]. Although, a prototype v-TFET has been experimentally fabricated and shown to have a steep slope [17], it still suffers from low ON current.…”

Section: Introductionmentioning

confidence: 99%

Switching Mechanism and the Scalability of Vertical-TFETs

Chen

Ilatikhameneh

Tan

et al. 2018

IEEE Trans. Electron Devices

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In this work, vertical tunnel field-effect transistors (v-TFETs) based on vertically stacked heretojunctions from 2D transition metal dichalcogenide (TMD) materials are studied by atomistic quantum transport simulations. The switching mechanism of v-TFET is found to be different from previous predictions. As a consequence of this switching mechanism, the extension region, where the materials are not stacked over is found to be critical for turning off the v-TFET. This extension region makes the scaling of v-TFETs challenging. In addition, due to the presence of both positive and negative charges inside the channel, v-TFETs also exhibit negative capacitance. As a result, v-TFETs have good energy-delay products and are one of the promising candidates for low power applications.

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Section: Introductionmentioning

confidence: 99%

Switching Mechanism and the Scalability of Vertical-TFETs

Chen

Ilatikhameneh

Tan

et al. 2018

IEEE Trans. Electron Devices

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“…The continuous scaling of MOSFETs has met tremendous challenges such as large leakage current, high power consumption. Novel material or transistor design have been shown to have promises in overcoming these challenges [1]- [6]. However, much more progress are still needed to realize large-scale manufacturing in such proposals [7], [8].…”

Section: Introductionmentioning

confidence: 99%

Hole mobility model for Si double-gate junctionless transistors

Fan

Wei

Sha

et al. 2017

2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)

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In this work, a physics based model is developed to calculate the hole mobility of ultra-thin-body double-gate junctionless transistors. Six-band k · p Schrödinger equation and Poisson equation are solved self-consistently. The obtained wavefunctions and energies are stored in look-up tables. Hole mobility can be derived using the Kubo-Greenwood formula accounting for impurity, acoustic and optical phonon, and surface roughness scattering. Initial benchmark results are shown.

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