IEEE Std 1581 &amp;#x2014; A standardized test access methodology for memory devices

Ehrenberg, H.; Russell, Bob

doi:10.1109/test.2011.6139141

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Cited by 4 publications

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“…For the sake of brevity, we focus on post-bond testing. In the past, (DRAM) memory vendors were typically not in favor of integrating JTAG on their devices [88]. Besides JTAG, other solutions have been proposed to test the interconnects.…”

Section: Test and Design-for-testmentioning

confidence: 99%

Challenges and Solutions in Emerging Memory Testing

Vatajelu

Prinetto

Taouil

et al. 2019

IEEE Trans. Emerg. Topics Comput.

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International audienceThe research and prototyping of new memory technologies are getting a lot of attention in order to enable new (computer) architectures and provide new opportunities for today’s and future applications. Delivering high quality and reliability products was and will remain a crucial step in the introduction of new technologies. Therefore, appropriate fault modelling, test development and design for testability (DfT) is needed. This paper overviews and discusses the challenges and the emerging solutions in testing three classes of memories: 3D stacked memories, Resistive memories and Spin-Transfer-Torque Magnetic memories. Defects mechanisms, fault models, and emerging test solutions will be discussed

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Section: Test and Design-for-testmentioning

confidence: 99%