iDocChip - A Configurable Hardware Architecture for Historical Document Image Processing: Text Line Extraction

Tekleyohannes, Menbere Kina; Rybalkin, Vladimir; Ghaffar, Muhammad Mohsin; Wehn, Norbert; Dengel, Andreas

doi:10.1109/reconfig48160.2019.8994761

Cited by 2 publications

(20 citation statements)

References 21 publications

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“…However, the software part of the hybrid architecture is very inefficient due to the inherently sequential union-find algorithm that is used for the connected component labeling (CCL) part of the Text and Image Segmentation chain. The presented accelerator in [7] has achieved nearly a 3Â gain in performance and more than 125Â increase in energy-efficiency compared to the original anyOCR implementation. In the current paper, this previous work is further optimized, and better performance and energy-efficiency are achieved (see Sect.…”

Section: Text and Image Segmentationmentioning

confidence: 98%

“…The research area for hardware acceleration of text and image segmentation has not been well investigated, which makes quantitative comparison difficult. However, in our previous work [7], we have presented, the first hardware architecture for multiresolution morphology-based text and image segmentation (see Sect. 3).…”

Section: Text and Image Segmentation Hardware Architecturesmentioning

confidence: 99%

“…1, the anyOCR pipeline includes layout analysis and character recognition steps. In our previous works [7,[39][40][41], hardware accelerators of these steps were introduced and implemented on Xilinx Zynq-7000 XC7Z045 SoC. The performance and energy-efficiency of each one of these accelerators were compared to the original Python-based anyOCR running on Intel Ò Core TM i7.…”

Section: Our Previous Workmentioning

confidence: 99%

“…This pipeline step separates the text and non-text parts of a document image, using a multiresolution morphology-based text and image segmentation method. The corresponding hybrid hardware-software architecture was presented in [7], which optimizes the original software algorithm of anyOCR in order to make it suitable for efficient hardware parallelization with negligible loss of accuracy. To exploit the hardware concurrency, time-critical operations with parallelization capability are implemented in the hardware fabric, while those operations that are inherently sequential are implemented in software, resulting in an efficient hardware-software partitioning of the text-image segmentation algorithm.…”

Section: Text and Image Segmentationmentioning

confidence: 99%

“…Hence, after analyzing the different parallelization schemes and studying the trade-offs between different types of memories on an FPGA, the best fitting hardware-software partitioning scheme is chosen. Accordingly, the first hybrid hardware-software architecture of the multiresolution morphology-based Text and Image Segmentation technique is developed [7] that is part of iDocChip. In this paper, we present the optimized FPGA-based hybrid architecture of this anyOCR step and its optimized software implementations.…”

Section: Introductionmentioning

confidence: 99%

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iDocChip: A Configurable Hardware Architecture for Historical Document Image Processing

Tekleyohannes

Rybalkin

Ghaffar

et al. 2021

Int J Parallel Prog

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In recent years, $$\hbox {optical character recognition (OCR)}$$ optical character recognition (OCR) systems have been used to digitally preserve historical archives. To transcribe historical archives into a machine-readable form, first, the documents are scanned, then an $$\hbox {OCR}$$ OCR is applied. In order to digitize documents without the need to remove them from where they are archived, it is valuable to have a portable device that combines scanning and $$\hbox {OCR}$$ OCR capabilities. Nowadays, there exist many commercial and open-source document digitization techniques, which are optimized for contemporary documents. However, they fail to give sufficient text recognition accuracy for transcribing historical documents due to the severe quality degradation of such documents. On the contrary, the anyOCR system, which is designed to mainly digitize historical documents, provides high accuracy. However, this comes at a cost of high computational complexity resulting in long runtime and high power consumption. To tackle these challenges, we propose a low power energy-efficient accelerator with real-time capabilities called iDocChip, which is a configurable hybrid hardware-software programmable $$\hbox {System-on-Chip (SoC)}$$ System-on-Chip (SoC) based on anyOCR for digitizing historical documents. In this paper, we focus on one of the most crucial processing steps in the anyOCR system: Text and Image Segmentation, which makes use of a multi-resolution morphology-based algorithm. Moreover, an optimized $$\hbox {FPGA}$$ FPGA -based hybrid architecture of this anyOCR step along with its optimized software implementations are presented. We demonstrate our results on multiple embedded and general-purpose platforms with respect to runtime and power consumption. The resulting hardware accelerator outperforms the existing anyOCR by 6.2$$\times$$ × , while achieving 207$$\times$$ × higher energy-efficiency and maintaining its high accuracy.

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Section: Text and Image Segmentationmentioning

confidence: 98%

Section: Text and Image Segmentation Hardware Architecturesmentioning

confidence: 99%

Section: Our Previous Workmentioning

confidence: 99%

Section: Text and Image Segmentationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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iDocChip: A Configurable Hardware Architecture for Historical Document Image Processing

Tekleyohannes

Rybalkin

Ghaffar

et al. 2021

Int J Parallel Prog

Self Cite

View full text Add to dashboard Cite

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iDocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

et al. 2021

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In recent years, there has been an increasing demand to digitize and electronically access historical records. Optical character recognition (OCR) is typically applied to scanned historical archives to transcribe them from document images into machine-readable texts. Many libraries offer special stationary equipment for scanning historical documents. However, to digitize these records without removing them from where they are archived, portable devices that combine scanning and OCR capabilities are required. An existing end-to-end OCR software called anyOCR achieves high recognition accuracy for historical documents. However, it is unsuitable for portable devices, as it exhibits high computational complexity resulting in long runtime and high power consumption. Therefore, we have designed and implemented a configurable hardware-software programmable SoC called iDocChip that makes use of anyOCR techniques to achieve high accuracy. As a low-power and energy-efficient system with real-time capabilities, the iDocChip delivers the required portability. In this paper, we present the hybrid CPU-FPGA architecture of iDocChip along with the optimized software implementations of the anyOCR. We demonstrate our results on multiple platforms with respect to runtime and power consumption. The iDocChip system outperforms the existing anyOCR by 44× while achieving 2201× higher energy efficiency and a 3.8% increase in recognition accuracy.

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iDocChip - A Configurable Hardware Architecture for Historical Document Image Processing: Text Line Extraction

Cited by 2 publications

References 21 publications

iDocChip: A Configurable Hardware Architecture for Historical Document Image Processing

iDocChip: A Configurable Hardware Architecture for Historical Document Image Processing

iDocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

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